Datasheet > THC63LVD824A

THC63LVD824A

更新时间： 2024-02-11 23:12:09

品牌	Logo	应用领域
THINE		/
页数	文件大小	规格书
14页	148K
描述
Single(112MHz)/Dual(170MHz) Link LVDS Receiver for XGA/SXGA/SXGA/UXGA

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技术参数
数据手册

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THC63LVD824A 技术参数

是否Rohs认证：	符合	生命周期：	Contact Manufacturer
Reach Compliance Code：	unknown	风险等级：	5.81
JESD-30 代码：	S-PQFP-G100	端子数量：	100
最高工作温度：	70 °C	最低工作温度：	-10 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装等效代码：	QFP100,.63SQ,20	封装形状：	SQUARE
封装形式：	FLATPACK	电源：	3.3 V
认证状态：	Not Qualified	子类别：	Line Driver or Receivers
最大压摆率：	225 mA	标称供电电压：	3.3 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD

THC63LVD824A 数据手册

THC63LVD824A _Rev1.20_E

THC63LVD824A

Single(112MHz)/Dual(170MHz) Link LVDS Receiver for XGA/SXGA/SXGA+/UXGA

General Description

Features

The THC63LVD824A receiver is designed to support

Single Link transmission between Host and Flat Panel

Display up to SXGA resolutions and Dual Link trans-

mission between Host and Flat Panel Display up to

UXGA resolutions. The THC63LVD824A converts the

LVDS data streams back into 48bits of CMOS/TTL data

with falling edge or rising edge clock for convenient

with a variety of LCD panel controllers.

•

Wide dot clock range: 25-170MHz suited for VGA,

SVGA, XGA, SXGA, SXGA+ and UXGA

•

PLL requires No external components

Supports Single Link up to 112MHz dot clock for

SXGA

•

Supports Dual Link up to 170MHz dot clock for

UXGA

In Single Link, data transmit clock frequency of

112MHz, 48bits of RGB data are transmitted at an

effective rate of 784Mbps per LVDS channel. Using a

112MHz clock, the data throughput is 392Mbytes per

second.

In Dual Link, data transmit clock frequency of 85MHz,

48bits of RGB data are transmitted at an effective rate

of 595Mbps per LVDS channel. Using a 85MHz clock,

the data throughput is 595Mbytes per second.

•

50% output clock duty cycle

TTL clock edge programmable

TTL output driverbility selectable for lower EMI

Power down mode

Low power single 3.3V CMOS design

100pin TQFP

THC63LVDF84B compatible

Pin compatible with THC63LVD824

Block Diagram

LVDS INPUT

RA1 +/-

CMOS/TTL OUTPUT

RED1

RB1 +/-

GREEN1

BLUE1

1st DATA

1st Link

RC1 +/-

RD1 +/-

HSYNC

VSYNC

RCLK1 +/-

(25 to 112MHz)

PLL

RECEIVER CLOCK OUT

(12.5 to 85MHz)

RA2 +/-

RB2 +/-

RC2 +/-

RD2 +/-

RED2

GREEN2

BLUE2

2nd DATA

2nd Link

RCLK2 +/-

(25 to 85MHz)

PLL

R/F

/PDWN

1/14

THine Electronics, Inc.

12 3 4 5 6 7...14

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