THC63LVD824A _Rev1.20_E
THC63LVD824A
Single(112MHz)/Dual(170MHz) Link LVDS Receiver for XGA/SXGA/SXGA+/UXGA
General Description
Features
The THC63LVD824A receiver is designed to support
Single Link transmission between Host and Flat Panel
Display up to SXGA resolutions and Dual Link trans-
mission between Host and Flat Panel Display up to
UXGA resolutions. The THC63LVD824A converts the
LVDS data streams back into 48bits of CMOS/TTL data
with falling edge or rising edge clock for convenient
with a variety of LCD panel controllers.
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Wide dot clock range: 25-170MHz suited for VGA,
SVGA, XGA, SXGA, SXGA+ and UXGA
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PLL requires No external components
Supports Single Link up to 112MHz dot clock for
SXGA
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Supports Dual Link up to 170MHz dot clock for
UXGA
In Single Link, data transmit clock frequency of
112MHz, 48bits of RGB data are transmitted at an
effective rate of 784Mbps per LVDS channel. Using a
112MHz clock, the data throughput is 392Mbytes per
second.
In Dual Link, data transmit clock frequency of 85MHz,
48bits of RGB data are transmitted at an effective rate
of 595Mbps per LVDS channel. Using a 85MHz clock,
the data throughput is 595Mbytes per second.
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50% output clock duty cycle
TTL clock edge programmable
TTL output driverbility selectable for lower EMI
Power down mode
Low power single 3.3V CMOS design
100pin TQFP
THC63LVDF84B compatible
Pin compatible with THC63LVD824
Block Diagram
LVDS INPUT
RA1 +/-
CMOS/TTL OUTPUT
8
RED1
8
RB1 +/-
GREEN1
BLUE1
1st DATA
28
8
1st Link
RC1 +/-
RD1 +/-
HSYNC
VSYNC
DE
RCLK1 +/-
(25 to 112MHz)
PLL
RECEIVER CLOCK OUT
(12.5 to 85MHz)
RA2 +/-
RB2 +/-
RC2 +/-
RD2 +/-
8
8
RED2
28
GREEN2
BLUE2
2nd DATA
2nd Link
8
RCLK2 +/-
(25 to 85MHz)
PLL
R/F
/PDWN
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THine Electronics, Inc.