Datasheet > DI2CM

DI2CM

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
DCD		/
页数	文件大小	规格书
5页	155K
描述
I2C Bus Interface - Master

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DI2CM 数据手册

DI2CM

I²C Bus Interface - Master

ver 3.08

● Build-in 8-bit timer for data transfers speed

O V E R V I E W

adjusting

I²C is a two-wire, bi-directional serial bus that

provides a simple and efficient method of data

transmission over a short distance between

many devices. The DI2CM core provides an

interface between a microprocessor / micro-

controller and an I²C bus. It can work as a

master transmitter or master receiver depend-

ing on working mode determined by micro-

processor/microcontroller. The DI2CM core

incorporates all features required by the latest

I²C specification including clock synchroniza-

tion, arbitration, multi-master systems and

High-speed transmission mode. Built-in timer

allows operation from a wide range of the clk

frequencies.

● Host side interface dedicated for micro-

processors/microcontrollers

● User-defined timing (data setup, start

setup, start hold, etc.)

● Fully synthesizable

● Static synchronous design with positive

edge clocking and synchronous reset

● No internal tri-states

● Scan test ready

A P P L I C A T I O N S

● Embedded microprocessor boards

● Consumer and professional audio/video

● Home and automotive radio

K E Y F E A T U R E S

● Conforms to v.2.1 of the I²C specification

● Master operation

● Low-power applications

○

Master transmitter

Master receiver

● Communication systems

● Cost-effective reliable automotive systems

● Support for all transmission speeds

D E L I V E R A B L E S

Source code:

◊ VHDL Source Code or/and

◊ VERILOG Source Code or/and

◊ Encrypted, or plain text EDIF netlist

VHDL & VERILOG test bench environ-

ment

○

Standard (up to 100 kb/s)

Fast (up to 400 kb/s)

♦

High Speed (up to 3,4 Mb/s)

● Arbitration and clock synchronization

● Support for multi-master systems

◊ Active-HDL automatic simulation macros

◊ ModelSim automatic simulation macros

◊ Tests with reference responses

Technical documentation

● Support for both 7-bit and 10-bit address-

ing formats on the I²C bus

♦

● Interrupt generation

◊ Installation notes

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

12 3 4 5

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