Datasheet > DI2CMS

DI2CMS

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
DCD		/
页数	文件大小	规格书
6页	161K
描述
I2C Bus Interface - Master/Slave

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DI2CMS 数据手册

DI2CMS

I²C Bus Interface – Master/Slave

ver 1.01

○

Support for all transmission speeds

O V E R V I E W

○ Standard (up to 100 kb/s)

I²C is a two-wire, bi-directional serial bus that

provides a simple and efficient method of data

transmission over a short distance between

many devices. The DI2CMS core provides an

interface between a microprocessor / micro-

controller and an I²C bus. It can work as a

master or slave transmitter/receiver depend-

ing on working mode determined by micro-

processor/microcontroller. The DI2CMS core

incorporates all features required by the latest

I²C specification including clock synchroniza-

tion, arbitration, multi-master systems and

High-speed transmission mode. The DI2CMS

supports all the transmission speed modes.

Built-in timer allows operation from a wide

range of the clk frequencies.

○ Fast (up to 400 kb/s)

○ High Speed (up to 3,4 Mb/s)

Arbitration and clock synchronization

Support for multi-master systems

○

Support for both 7-bit and 10-bit addressing

formats on the I²C bus

○

Build-in 8-bit timer for data transfers speed

adjusting

User-defined timing (data setup, start setup,

start hold, etc.)

● Slave mode

○

Slave operation

○ Slave transmitter

The DI2CMS is a technology independent

VHDL or VERILOG design that can be imple-

mented in a variety of process technologies

and can be fully customized accordingly to

customer needs.

○ Slave receiver

Supports 3 transmission speed modes

○ Standard (up to 100 kb/s)

○ Fast (up to 400 kb/s)

DI2CMS is delivered with fully automated

testbench and complete set of tests allow-

ing easy package validation at each stage of

SoC design flow.

○ High Speed (up to 3,4 Mb/s)

○

Allows operation from a wide range of input

clock frequencies

User-defined data setup time

K E Y F E A T U R E S

● Conforms to v.2.1 of the I²C specification

● Simple interface allows easy connection to

microprocessor/microcontroller devices

● Master mode

● Interrupt generation

● Fully synthesizable

○

Master operation

○ Master transmitter

○ Master receiver

● Static synchronous design with positive

edge clocking and synchronous reset

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

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