Datasheet > MT46V16M8

MT46V16M8

更新时间： 2022-11-25 21:39:52

品牌	Logo	应用领域
镁光 - MICRON		动态存储器双倍数据速率
页数	文件大小	规格书
9页	167K
描述
DOUBLE DATA RATE DDR SDRAM

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

MT46V16M8 数据手册

PREVIEW^‡

128Mb: x8

DDR400 SDRAM Addendum

MT46V16M8 – 4 Meg x 8 x 4 banks

DOUBLE DATA RATE

(DDR) SDRAM

For the latest data sheet revisions, please refer to the Micron

Website:www.micron.com/dramds

FEATURES

GENERAL DESCRIPTION

• 200 MHz Clock, 400 Mb/s/p data rate

• V^DD= +2.65V 0.ꢀ0V

The DDR400 SDRAM is a high-speed CMOS, dy-

namic random-access memory that operates at a fre-

quency of 200 MHz (^tCK=5ns) with a peak data transfer

rate of 400Mb/s. DDR400 continues to use the JEDEC

standard SSTL_2 interface and the 2n-prefetch archi-

tecture.

• VDDQ = +2.65V 0.ꢀ0V

• Bidirectional data strobe (DQS) transmitted/

received with data, i.e., source-synchronous data

capture

• Internal, pipelined double-data-rate (DDR)

architecture; two data accesses per clock cycle

• Differential clock inputs (CK and CK#)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

The standard DDR200/DDR266 data sheets also

pertain to the DDR400 device and should be refer-

enced for a complete description of DDR SDRAM func-

tionality and operating modes. However, to meet the

faster DDR400 operating frequencies, some of the AC

timing parameters, DC levels and operating tempera-

tures are slightly tighter. This addendum data sheet

will concentrate on the key differences required to sup-

port the enhanced speeds.

• DLL to align DQ and DQS transitions with CK

• Four internal banks for concurrent operation

• Data mask (DM) for masking write data

• Programmable burst lengths: 2, 4, or 8

• Concurrent Auto Precharge option supported

• Auto Refresh and Self Refresh Modes

The Micron 128Mb data sheet provides full specifica-

tions and functionality unless specified herein.

• RAS lockout (^tRAP = RCD)

CONFIGURATION

Architecture

OPTIONS

• Configuration

PARTNUMBER

16 Meg x 8

4 Meg x 8 x 4 banks

ꢀ6 Meg x 8 (4 Meg x 8 x 4 banks)

ꢀ6M8

Configuration

Refresh Count

• Plastic Package

Row Addressing

Bank Addressing

Column Addressing

4K (A0–A11)

4 (BA0, BA1)

1K (A0–A9)

66-Pin TSOP

(400mil with 0.65mm pin pitch)

• Timing - Cycle Time

5ns @ CL = 3^(ꢀ)

-5

• Self Refresh

Standard

none

KEYTIMINGPARAMETERS

SPEED

GRADE

-5

CLOCK RATE

CL = 3¹

DATA-OUT ACCESS DQS-DQ

WINDOW²WINDOW SKEW

NOTE: 1. Supports modules with 3-4-4 timing

200MHz

2.15ns

0.50ns +0.35ns

NOTE: 1. CL = CAS (Read) Latency

2. With a 50/50 clock duty cycle

128Mb: x8DDR400 SDRAM

128Mbx8DDR400.p65 – Rev. A (1/30/02-B)

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

‡

THIS DATA SHEET CONTAINS THE PRESENT DESCRIPTION OF A PRODUCT IN DEFINITION WITH NO FORMAL DESIGN IN PROGRESS.

12 3 4 5 6 7...9

下载PDF

与MT46V16M8相关器件

型号	品牌	描述	获取价格	数据表
MT46V16M8TG-75	MICRON	DOUBLE DATA RATE DDR SDRAM	获取价格
MT46V16M8TG-75L	MICRON	DOUBLE DATA RATE DDR SDRAM	获取价格
MT46V16M8TG-75Z	MICRON	DOUBLE DATA RATE DDR SDRAM	获取价格
MT46V16M8TG-75ZL	MICRON	DOUBLE DATA RATE DDR SDRAM	获取价格
MT46V16M8TG-8	MICRON	DOUBLE DATA RATE DDR SDRAM	获取价格
MT46V16M8TG-8L	MICRON	DOUBLE DATA RATE DDR SDRAM	获取价格