512Mb: x4, x8, x16 DDR SDRAM
Features
Double Data Rate (DDR) SDRAM
MT46V128M4 – 32 Meg x 4 x 4 banks
MT46V64M8 – 16 Meg x 8 x 4 banks
MT46V32M16 – 8 Meg x 16 x 4 banks
Features
Options
Marking
• V = 2.5V ±±.2V, V
= 2.5V ±±.2V
DDQ
• Configuration
DD
1
V
= 2.6V ±±.1V, V
= 2.6V ±±.1V (DDR4±±)
– 128 Meg x 4 (32 Meg x 4 x 4 banks)
– 64 Meg x 8 (16 Meg x 8 x 4 banks)
– 32 Meg x 16 (8 Meg x 16 x 4 banks)
• Plastic package
128M4
64M8
32M16
DD
DDQ
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
– 66-pin TSOP
TG
P
– 66-pin TSOP (Pb-free)
– 6±-ball FBGA (1±mm x 12.5mm)
– 6±-ball FBGA (1±mm x 12.5mm) (Pb-free)
– 6±-ball FBGA (8mm x 12.5mm)
– 6±-ball FBGA (8mm x 12.5mm) (Pb-free)
• Timing – cycle time
2
FN
2
3
BN
CV
CY
3
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data ꢀ
(x16 has two – one per byte)
• Programmable burst lengths: 2, 4, or 8
• Auto refresh
– 64ms, 8192-cycle
• Longer-lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
– 5ns @ CL = 3 (DDR4±±)
– 6ns @ CL = 2.5 (DDR333) (FBGA only)
– 6ns @ CL = 2.5 (DDR333) (TSOP only)
• Self refresh
– Standard
– Low-power self refresh
• Temperature rating
– Commercial (±°C to +7±°C)
– Industrial (–4±°C to +85°C)
• Revision
– x4, x8, x16
– x4, x8, x16
-5B
2
-6
-6T
2
None
L
None
IT
• Concurrent auto precharge option is supported
:F
:J
t
t
t
• RAS lockout supported ( RAP = RCD)
Notes: 1. DDR4±± devices operating at < DDR333ꢀ
conditions can use V /V = 2.5V +±.2V.
DD DDQ
2. Available only on Revision F.
3. Available only on Revision J.
Table 1:
Key Timing Parameters
CL = CAS (READ) latency; data-out window is MIN clock rate with 50% duty cycle at CL = 2, CL = 2.5, or CL = 3
Clock Rate (MHz)
Speed
Grade
Data-Out
Window
Access
Window
DQS–DQ
Skew
CL = 2
CL = 2.5
CL = 3
-5B
-6
133
133
133
133
100
167
167
167
133
133
200
n/a
n/a
n/a
n/a
1.6ns
2.1ns
2.0ns
2.5ns
2.5ns
0.70ns
0.70ns
0.70ns
0.75ns
0.75ns
0.40ns
0.40ns
0.45ns
0.50ns
0.50ns
6T
-75E/-75Z
-75
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
512Mb_DDR_x4x8x16_D1.fm - 512Mb DDR: Rev. Q; Core DDR Rev. E 7/11 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.ꢀ
1
©2000 Micron Technology, Inc. All rights reserved.
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