W3H264M16E-XB2X
*PRELIMINARY
256MB – 2 x 64M x 16 DDR2 SDRAM 79 PBGA
FEATURES
BENEFITS
Data rate = 400, 533 and 667 Mb/s
Larger ball pitch for higher reliability
Package:
Footprint compatible with W3H64M16E
• 79 Plastic Ball Grid Array (PBGA), 11 x 14mm
• 1.27mm pitch
* This product is under development, is not qualified or characterized and is subject to change
without notice.
• Moisture Sensitivity Level (MSL): 3
Supply Voltage = 1.8V
Differential data strobe (DQS, DQS#) per byte
Internal, pipelined, double data rate architecture
4-bit prefetch architecture
TYPICAL APPLICATION
DLL for alignment of DQ and DQS transitions with clock
signal
Eight internal banks for concurrent operation
Programmable Burst lengths: 4 or 8
RAM
Auto Refresh and Self Refresh Modes
On Die Termination (ODT)
DDR2/DDR3
W3H264M16E-XBI
Host
FPGA/
Adjustable data – output drive strength
Programmable CAS latency: 3, 4, 5, 6, or 7
Posted CAS additive latency: 0, 1, 2, 3, 4, 5, or 6
Write latency = Read latency – 1* tCK
Commercial, Industrial and Military Temperature Ranges
Organized as 2 ranks of 64M x 16
Processor
SSD (SLC)
MSM32/MSM64 (SATA BGA)
W7N16GVHxxBI (PATA BGA)
M512/M256/M128 (SATA, 2.5in)
Weight: W3H264M16E-XB2X – TBD
Microsemi Corporation reserves the right to change products or specifications without notice.
March 2016 © 2016 Microsemi Corporation. All rights reserved.
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Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp