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PL613-01-XXXQI-TR PDF预览

PL613-01-XXXQI-TR

更新时间： 2024-02-27 07:41:53
品牌 Logo 应用领域
美国微芯 - MICROCHIP 时钟外围集成电路
页数 文件大小 规格书
20页 591K
描述
Clock Generator

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PL613-01-XXXQI-TR 技术参数

生命周期：Active包装说明：HVQCCN, LCC16,.12SQ,20
Reach Compliance Code：compliant风险等级：5.19
JESD-30 代码：S-XQCC-N16长度：3 mm
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C最大输出时钟频率：200 MHz
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装等效代码：LCC16,.12SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE座面最大高度：0.85 mm
最大压摆率：23 mA最大供电电压：3.63 V
最小供电电压：1.62 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD宽度：3 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHERBase Number Matches：1

PL613-01-XXXQI-TR 数据手册

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PL613-01  
1.8V to 3.3V, PicoPLL, 3-PLL, 200 MHz, 8 Output Clock IC  
Features  
General Description  
• Designed for PCB Space Savings with Three  
Low-Power Programmable PLLs and up to 8  
Clock Outputs  
The PL613-01 is an advanced triple PLL design based  
on Microchip’s PicoPLL™, the world’s smallest  
programmable clock, technology. This advanced  
technology allows the eight output PL613-01 to fit in to  
a small 3 mm x 3 mm QFN or TSSOP package for high  
performance, low-power, low-cost applications.  
Besides its small form factor and 8 outputs that can  
reduce overall system costs, the PL613-01 offers  
superior phase noise, jitter and power consumption  
performance.  
• Low Power Consumption  
- 10 µA Typical When PDB is Activated  
• Output Frequency:  
- ≤110 MHz at 1.8V Operation  
- ≤166 MHz at 2.5V Operation  
- ≤200 MHz at 3.3V Operation  
• Input Frequency:  
The power down feature of PL613-01, when activated,  
allows the IC to consume less than 10 µA of power,  
while its CSEL[0:1] allows switching between up to four  
pre-programmed configurations. The FSELX, on the  
other hand, allows frequency switching of two outputs  
(CLK1 and CLK2) on a single clock pin (CLK2).  
- Fundamental Crystal: 10 MHz to 40 MHz  
- Reference Input: 10 MHz to 200 MHz  
• Programmable I/O Pins Can be Configured as  
Output Enable (OE), Configuration Switching  
(CSEL), Frequency Switching (FSELX), Power  
Down (PDB) Inputs, or Clock Outputs  
• Disabled Outputs Programmable as HiZ or Active  
Low  
• Four Distinct Configurations Selectable with  
CSEL[0:1]  
• Single 1.8V, 2.5V, or 3.3V ±10% Power Supply  
• Temperature range: 0°C to 70°C, –40°C to +85°C  
• Available in 3 mm x 3 mm QFN or TSSOP  
Packages  
Block Diagram  
PL613-01  
FREF  
Odd/Even  
Divider  
CLK2  
VCO1  
XIN/FIN  
XOUT  
FREF  
Programmable  
PLL1  
Xtal  
OSC  
(5-bits)  
÷1, ÷2,  
÷4, ÷8  
CLK3, OE4  
Odd/Even  
Divider  
CLK4  
(5-bits)  
FREF  
OE, OEM  
CSEL[0:1]  
Odd/Even  
Divider  
CLK1, OE2  
(5-bits)  
VCO2  
Programmable  
PLL2  
÷1, ÷2,  
÷4, ÷8  
FSELX  
PDB  
Output Drive  
CLK0, FSELX  
Odd/Even  
Divider  
(5-bits)  
CLK7, OE0, CSEL1  
FREF  
Odd/Even  
Divider  
(5-bits)  
VCO3  
CLK5, OE6, CSEL0  
CLK6, OEM, PDB  
Programmable  
PLL3  
÷1, ÷2,  
÷4, ÷8  
Programmable Function  
2016 Microchip Technology Inc.  
DS20005650A-page 1  
1234567...20

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