Datasheet > PCS3I623Z05AG-16-TT

PCS3I623Z05AG-16-TT

更新时间： 2023-07-15 00:00:00

品牌	Logo	应用领域
PULSECORE		光电二极管
页数	文件大小	规格书
15页	1380K
描述
Clock Generator, 50MHz, CMOS, PDSO16, 4.40 MM, GREEN, TSSOP-16

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PCS3P623Z05A/B and PCS3P623Z09A/B

Timing-Safe™ Peak EMI

Reduction IC

General Features

Functional Description

PCS3P623Z05/09 is a versatile, 3.3V Zero-delay buffer

designed to distribute Timing-Safe™ clocks with Peak EMI

reduction. PCS3P623Z05 is an eight-pin version, accepts

one reference input and drives out five low-skew Timing-

Safe™ clocks. PCS3P623Z09 accepts one reference input

and drives out nine low-skew Timing-Safe™clocks.

• Clock distribution with Timing-Safe™ Peak EMI

Reduction

• Input frequency range: 20MHz - 50MHz

• Multiple low skew Timing-safe™ Outputs:

PCS3P623Z05: 5 Outputs

PCS3P623Z09: 9 Outputs

PCS3P623Z05/09 has a DLY_CTRL for adjusting the

Input-Output clock delay, depending upon the value of

capacitor connected at this pin to GND.

• External Input-Output Delay Control option

• Supply Voltage: 3.3V±0.3V

• Commercial and Industrial temperature range

• Packaging Information:

PCS3P623Z05/09 operates from a 3.3V supply and is

available in two different packages, as shown in the

ordering information table, over commercial and Industrial

temperature range.

ASM3P623Z05: 8 pin SOIC, and TSSOP

ASM3P623Z09:16 pin SOIC, and TSSOP

• True Drop-in Solution for Zero Delay Buffer,

ASM5P2305A / 09A

Application

PCS3P623Z05/09 is targeted for use in Displays and

memory interface systems.

General Block Diagram

DLY_CTRL

PLL

DLY_CTRL

PLL

MUX

CLKIN

CLKOUTA1

CLKOUTA2

CLKOUTA3

CLKOUT1

CLKOUT2

CLKOUT3

CLKIN

CLKOUTA4

CLKOUTB1

PCS3P623Z05A/B

CLKOUT4

Select Input

Decoding

CLKOUTB2

CLKOUTB3

CLKOUTB4

PCS3P623Z09A/B

January 2010 – Rev. 1

Publication Order Number:

PCS3P623Z05/D

12 3 4 5 6 7...15

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PCS3I623Z09AG-08-ST	ONSEMI	50MHz, OTHER CLOCK GENERATOR, PDSO16, 0.150 INCH, GREEN, SOIC-16	获取价格