32GB (x72, DR) 288-Pin DDR5 ECC UDIMM
Features
DDR5 SDRAM EUDIMM Addendum
MTC20C2085S1EC – 32GB
16Gb Die Revision A
Features
Options
Marking
Information provided here is in addition to or super-
sedes information provided in the Micron DDR5
UDIMM Core data sheet.
• Operating temperature
– Commercial (0°C ≤ TOPER ≤ 95°C)
• Frequency/CAS latency
C
48B
– 0.416ns @ CL = 40 (DDR5-4800)
• DDR5 functionality and operations supported as
defined in the component data sheet
Figure 1: 288-Pin DDR5 EUDIMM (R/C-E0)
• Features and specifications defined in the Micron
DDR5 UDIMM core data sheet
U1
• 288-pin, DDR5 unbuffered ECC dual in-line memory
U2
module (DDR5 EUDIMM)
• Fast data transfer rate: PC5-4800
• 32GB (4Gig x 72)
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12
Primary side
• Dual-rank
• 32 internal banks; 8 groups of 4 banks each
• Supports ECC error detection and correction
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
Secondary side
Table 1: Addressing
Parameter
32GB
Row address 1
64K (R0-R15)
1K (C0-C9)
Column address 1
Device bank group address 1
8 (BG0-BG2)
4 (BA0-BA1)
Device bank address per bank group 1
Device configuration
16Gb (2Gb x 8), 32 banks
2 (CS0_n, CS1_n)
Module rank address
Notes: 1. These parameters represent the logical address state of the CA bus for different commands. Refer to the command
truth table in the component data sheet.
Table 2: Part Numbers and Timing Parameters – 32GB Modules
Clock Cycles
(CL-nRCD-nRP)
Module
Density
Module
Bandwidth
Memory Clock/
Data Rate
Part Number
Configuration
MTC20C2085S1EC48BA1
32GB
4Gb x 72
38.4 GB/s
0.416ns/4800 MT/s
40-39-39
Notes: 1. Base device: MT60B2G8, 16Gb DDR5 SDRAM Die Revision A. The data sheet for the base device can be found on
micron.com.
CCM005-802248454-36
mtc20c2085s1ec_drx8_eudimm_dierevA.pdf - Rev. B 12/2022
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1
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Products and specifications discussed herein are subject to change by Micron without notice.