Short Form Data Sheet
August 2014
MAX24705, MAX24710
5- or 10-Output Any-to-Any Line Card Timing ICs
with Internal EEPROM
General Description
Features
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Input Clocks
The MAX24705 and MAX24710 are flexible, high-
performance timing and clock synthesizer ICs that
include a DPLL and two independent APLLs. When
locked to one of two input clock signals, the device
performs any-to-any frequency conversion. From any
input clock frequency 1Hz to 750MHz the device can
produce frequency-locked APLL output frequencies up
to 750MHz and as many as 10 output clock signals that
are integer divisors of the APLL frequencies. Input jitter
can be attenuated by an internal low-bandwidth DPLL.
The DPLL also provides truly hitless switching between
input clocks and a high-resolution holdover capability.
Input switching can be manual or automatic. Using only
a low-cost crystal or oscillator, the device can also serve
as a frequency synthesizer IC. Output jitter is typically
0.18 to 0.3ps RMS for an APLL-only integer multiply
and 0.25 to 0.4ps RMS for APLL-only fractional multiply
or DPLL+APLL operation.
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One Crystal Input
Two Differential or CMOS/TTL Inputs
Differential to 750MHz, CMOS/TTL to 160MHz
Continuous Input Clock Quality Monitoring
Automatic or Manual Clock Selection
Hitless Reference Switching on Loss of Input
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Low-Bandwidth DPLL
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Programmable Bandwidth, 4Hz to 400Hz
Attenuates Jitter up to Several UI
Free-Run or Holdover on Loss of All Inputs
Hitless Reference Switching on Loss of Input
Manual Phase Adjustment
Two APLLs Plus 5 or 10 Output Clocks
For telecom systems, the device has all required
features and functions to serve as a line card timing IC.
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APLLs Perform High Resolution Fractional-N
Clock Multiplication
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Any Output Frequency from <1Hz to 750MHz
Each Output Has an Independent Divider
Applications
Frequency Conversion and Synthesis Applications in a
Wide Variety of Equipment Types
Output Jitter Typically 0.18 to 0.3ps RMS for
APLL-Only Integer Multiply and 0.25 to 0.4ps
RMS for Other Modes (12kHz to 20MHz)
Telecom Line Cards for SONET/SDH, Synchronous
Ethernet and Similar Applications
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Outputs are CML or 2xCMOS, Can Interface to
LVDS, LVPECL, HSTL, SSTL and HCSL
CMOS Output Voltage from 1.5V to 3.3V
Ordering Information
TEMP
PIN-
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General Features
PART
OUTPUTS
RANGE
PACKAGE
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Suitable Line Card IC for Stratum 2/3E/3/4E/4,
SMC, SEC/EEC, or SSU
MAX24705EXG+
MAX24710EXG+
5
-40 to +85
-40 to +85
81-CSBGA
81-CSBGA
10
Automatic Self-Configuration at Power-Up
from Internal EEPROM Memory
+Denotes a lead(Pb)-free/RoHS-compliant package.
Uses External Crystal, Oscillator or Clock
Signal As Master Clock
Internal Compensation for Local Oscillator
Frequency Error
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SPI Processor Interface
1.8V + 3.3V Operation (5V Tolerant)
-40°C to +85°C Operating Temp. Range
10mm x 10mm CSBGA Package
1