Renesas LSIs
M6MGB/T64BS8AWG-P
67,108,864-BIT (4,194,304-WORD BY 16-BIT) CMOS FLASH MEMORY
8,388,608-BIT (524,288-WORD BY 16-BIT) CMOS SRAM
&
Stacked-CSP (Chip Scale Package)
Description
The RENESAS M6MGB/T64BS8AWG-P is suitable for a
high performance cellular phone and a mobile PC that are
required to be small mounting area, weight and small power
dissipation.
The RENESAS M6MGB/T64BS8AWG-P is a Stacked Chip
Scale Package (S-CSP) that contents 64M-bit Flash memory
and 8M-bit SRAM in a 67-pin Stacked CSP with leaded
solder ball.
64M-bit Flash memory is a 4,194,304 words, single power
supply and high performance non-volatile memory fabricated
by CMOS technology for the peripheral circuit and DINOR IV
(Divided bit-line NOR IV) architecture for the memory cell. All
memory blocks are locked and can not be programmed or
erased, when F-WP# is Low. Using Software Lock Release
function, program or erase operation can be executed.
Features
Access Time
Flash
SRAM
70ns (Max.)
85ns (Max.)
F-VCC =S-VCC=2.7 ~ 3.0V
Ta= -40 ~ 85 degree
67pin S-CSP,
Supply Voltage
Ambient Temperature
Package
Ball pitch 0.80mm
Outer-ball:Sn - Pb
8M-bit SRAM is a 524,288 words asynchronous SRAM
fabricated by CMOS technology for the peripheral circuit and
TFT type transistor for the memory cell.
Application
Mobile communication products
PIN CONFIGURATION (TOP VIEW)
INDEX(Laser Marking)
8
4
5
6
7
1
2
3
NC
NC
A
NC
NC
NC
B
C
D
S-
F-
S-
F-
A20
A11
A16
A8
A18
LB#
WP#
GND
WE#
F-
RY/BY#
S-
UB#
F-
RP#
A5
A4
NC
A19
A17
A7
S-
OE#
A10
A15
A14
A21
E
F
G
H
J
A0
A6
A9
DQ11
F-
CE#
DQ13 DQ15
A3
A2
DQ9
DQ8
DQ0
DQ12
A13
A12
S-
CE2
S-
WE#
F-
GND
DQ10
DQ2
DQ6
F-
OE#
F-
GND
S-
VCC
DQ4
DQ5
DQ14
DQ7
A1
S-
CE1#
F-
VCC
NC
NC
DQ1
DQ3
NC
NC
K
L
NC
NC
M
(Top View)
8.5 mm
F-VCC
S-VCC
: VCC for Flash Memory
: VCC for SRAM
: GND for Flash Memory
: GND for SRAM
: Common address for Flash/SRAM
: Address for Flash
: Data I/O
: Flash chip enable
: SRAM chip enable1
: SRAM chip enable2
F-OE#
:Output enable for Flash
:Output enable for SRAM
:Write enable for Flash
:Write enable for SRAM
:Write protect for Flash
:Reset power down for Flash
:Flash Ready/Busy
:Lower byte control for SRAM
:Upper byte control for SRAM
:Non Connection
S-OE#
F-WE#
S-WE#
F-WP#
F-RP#
F-RY/BY#
S-LB#
S-UB#
NC
F-GND
S-GND
A0-A18
A19-A21
DQ0-DQ15
F-CE#
S-CE1#
S-CE2
1
Rev.1.0.48a_bebz