JLC1563 is an I2C–bus signal transceiver and “conditioner’’.
Currently, systems complexity and I2C–bus device types and
functionality are only increasing. As a result of I2C–bus loading the
Clock line and Data line signals degrade. The JLC1563 I2C–Bus
Transceiver restores clean signals in the system leading to
improvements in system performance and reliability.
http://onsemi.com
This device has two pins, SCL1 (Serial Clock Input) and SDA1
(Serial Data I/O), on the Master I2C–bus side; and two pins, SCL2
(Serial Clock Output) and SDA2 (Serial Data I/O), on the Slave
I2C–bus side.
HIGH–PERFORMANCE CMOS
LOW–POWER COMPLEMENTARY
MOS SILICON–GATE
Two reset pins, Reset1 and Reset2, drive separate internal
comparators and a system Power–On–Reset function is supported.
MARKING
DIAGRAMS
Features
• Low Power Dissipation
• Two Pin Reset/Power–On–Reset
• Waveform Cleaning
8
JLC1563P
AWL
YYWW
PDIP–8
P SUFFIX
CASE 626
8
1
1
8
1
SOEIAJ–8
M SUFFIX
CASE 968
1563
ALYW
8
1
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
JLC1563P
PDIP–8
50 Units/Rail
See Note 1.
See Note 1.
JLC1563M
JLC1563ML1
SOEIAJ–8
SOEIAJ–8
1. FororderinginformationontheEIAJversionofthe
SOIC packages, please contact your local ON
Semiconductor representative.
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
June, 2000 – Rev. 0
JLC1563/D