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Datasheet > IS61SP12832-166B
IS61SP12832-166B PDF预览

IS61SP12832-166B

更新时间： 2024-02-29 18:48:19
品牌 Logo 应用领域
矽成 - ICSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
14页 486K
描述
Standard SRAM, 128KX32, 3.5ns, CMOS, PQFP100,

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IS61SP12832-166B 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：BGA, BGA119,7X17,50针数：119
Reach Compliance Code：not_compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.9
最长访问时间：3.5 ns其他特性：SELF-TIMED WRITE; BURST COUNTER; BYTE WRITE; LINEAR/INTERLEAVED BURST SEQUENCE
最大时钟频率 (fCLK)：166 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B119JESD-609代码：e0
长度：22 mm内存密度：4194304 bit
内存集成电路类型：CACHE SRAM内存宽度：32
功能数量：1端子数量：119
字数：131072 words字数代码：128000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：128KX32
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA119,7X17,50
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL峰值回流温度（摄氏度）：240
电源：3.3 V认证状态：Not Qualified
座面最大高度：2.41 mm最大待机电流：0.005 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.23 mA最大供电电压 (Vsup)：3.63 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

IS61SP12832-166B 数据手册

 浏览型号IS61SP12832-166B的Datasheet PDF文件第2页浏览型号IS61SP12832-166B的Datasheet PDF文件第3页浏览型号IS61SP12832-166B的Datasheet PDF文件第4页浏览型号IS61SP12832-166B的Datasheet PDF文件第5页浏览型号IS61SP12832-166B的Datasheet PDF文件第6页浏览型号IS61SP12832-166B的Datasheet PDF文件第7页 
IS61SP12832  
128K x 32 SYNCHRONOUS  
PIPELINED STATIC RAM  
FEATURES  
DESCRIPTION  
The ICSI IS61SP12832 is a high-speed, low-power synchro-  
nous static RAM designed to provide a burstable, high-perfor-  
mance, secondary cache for the Pentium™, 680X0™, and  
PowerPC™ microprocessors. It is organized as 131,072  
words by 32 bits, fabricated with ICSI's advanced CMOS  
technology. The device integrates a 2-bit burst counter, high-  
speed SRAM core, and high-drive capability outputs into a  
single monolithic circuit. All synchronous inputs pass through  
registers controlled by a positive-edge-triggered single clock  
input.  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Pentium™ or linear burst sequence control  
using MODE input  
• Three chip enables for simple depth expansion  
and address pipelining  
• Common data inputs and data outputs  
• JEDEC 100-Pin LQFP and  
119-pin PBGA package  
• Single +3.3V, +10%, –5% power supply  
• Power-down snooze mode  
Write cycles are internally self-timed and are initiated by the  
rising edge of the clock input. Write cycles can be from one to  
four bytes wide as controlled by the write control inputs.  
Separate byte enables allow individual bytes to be written.  
BW1 controls DQa, BW2 controls DQb, BW3 controls DQc,  
BW4 controls DQd, conditioned by BWE being LOW. A LOW  
on GW input would cause all bytes to be written.  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller) input  
pins. Subsequent burst addresses can be generated internally  
by the IS61SP12832 and controlled by the ADV (burst address  
advance) input pin.  
The mode pin is used to select the burst sequence order,  
Linear burst is achieved when this pin is tied LOW. Interleave  
burst is achieved when this pin is tied HIGH or left floating.  
FAST ACCESS TIME  
Symbol  
Parameter  
-166  
3.5  
6
-150  
3.8  
6.7  
-133  
4
7.5  
133  
-117  
4
8.5  
117  
-5  
5
10  
100  
Units  
ns  
ns  
tKQ  
Clock Access Time  
Cycle Time  
tKC  
Frenquency  
166  
150  
MHz  
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors  
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.  
Integrated Circuit Solution Inc.  
1
SSR011-0B  
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与IS61SP12832-166B相关器件

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