Datasheet > IDT77V1253L25PGI8

IDT77V1253L25PGI8

更新时间： 2024-01-11 16:01:50

品牌	Logo	应用领域
艾迪悌 - IDT		ATM 异步传输模式
页数	文件大小	规格书
44页	454K
描述
ATM Network Interface, 1-Func, CMOS, PQFP144, 28 X 28 MM, PLASTIC, QFP-144

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TRIPLE PORT PHY (PHYSICAL LAYER)

IDT77V1253

FOR 25.6 AND 51.2 MBPS ATM NETWORKS

FEATURES:

DESCRIPTION:

• Performs the PHY-Transmission Convergence (TC) and Physical

Media Dependent (PMD) Sublayer functions for three 25.6 Mbps

ATMchannels

• Compliant to ATM Forum (af-phy-040.000) and ITU-T I.432.5

specifications for 25.6 Mbps physical interface

• Also operates at 51.2Mbps

The IDT77V1253 is a member of IDT's family of products supporting

AsynchronousTransferMode(ATM)datacommunicationsandnetworking.

TheIDT77V1253implementsthephysicallayerfor25.6MbpsATM,connect-

ingthreeserialcopperlinks(UTPCategory3)tooneATMlayerdevicesuch

asaSARoraswitchASIC. TheIDT77V1253alsooperatesat51.2Mbps,and

iswellsuitedtobackplanedrivingapplications.

• UTOPIA Level 1, UTOPIA Level 2, or DPI-4 Interface

• 3-Cell Transmit & Receive FIFOs

• LED Interface for status signalling

The 77V1253-to-ATMlayerinterfaceisselectableasoneofthreeoptions:

16-bit UTOPIA Level 2, 8-bit UTOPIA Level 1 Multi-PHY, or triple 4-bit DPI

(DataPathInterface).

• Supports UTP Category 3 physical media

• Interfaces to standard magnetics

TheIDT77V1253isfabricatedusingIDT'sstate-of-the-artCMOStechnol-

ogy,providingthehighestlevelsofintegration,performanceandreliability,with

thelow-powerconsumptioncharacteristicsofCMOS.

• Low-Power CMOS

• 3.3V supply with 5V tolerant inputs

• 144-pin PQFP Package (28 x 28 mm)

FUNCTIONAL BLOCK DIAGRAM - UTOPIA LEVEL 2 MODE

TxREF

TxCLK

TxDATA[15:0]

Driver

Tx 0

Rx 0

TxPARITY

TxSOC

5B/4B

Encoding/

Decoding

Tx/Rx ATM

Cell FIFO

Scrambler/

Descrambler

P/S and S/P

NRZI

Clock/Data

Recovery

TxEN

TxCLAV

TxADDR[4:0]

PHY-ATM

Interface

MODE[1:0]

(UTOPIA or DPI)

RxADDR[4:0]

RxCLK

RxDATA[15:0]

RxPARITY

RxSOC

Driver

Tx 1

Rx 1

5B/4B

Encoding/

Decoding

Tx/Rx ATM

Cell FIFO

Scrambler/

Descrambler

P/S and S/P

NRZI

Clock/Data

Recovery

RxEN

RxCLAV

INT

RST

Driver

Microprocessor

(Utility Bus)

Interface

Tx 2

Rx 2

5B/4B

Encoding/

Decoding

Tx/Rx ATM

Cell FIFO

Scrambler/

Descrambler

P/S and S/P

NRZI

Clock/Data

Recovery

AD[7:0]

ALE

OSC

RxREF

RxLED[2:0] TxLED[2:0]

4781 drw 01

DECEMBER 2004

IDTandtheIDTlogoaretrademarksofIntegratedDeviceTechnology,Inc.



DSC-4781/2

12 3 4 5 6 7...44

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