HDTV
Deserialiser
GD14516A
Advance Information
The GD14516A High Definition TV
Deserialiser is designed for point-to-point
serial transmission systems for HDTV
signals according to SMPTE292.
quency is more than 500 ppm away from
the REFCK frequency, the LDC switches
to the local clock (REFCK) until the VCO
frequency once more enters the
Features
Nominal data-rate 1485 Mbit/s NRZI.
±500 ppm range. Then it switches back
to the PD, comparing the VCO clock to
the incoming data stream. The LDC con-
tinuously monitors the VCO frequency
against the REFCK input, clearing LOCK
if the VCO leaves the lock range.
The device provides a fully integrated
solution for:
Two operating ranges:
–
–
1.2 -1.5 Gbit/s
300 - 375 Mbit/s
Clock recovery and data re-timing at
1485 Mbit/s
Descrambler and NRZI decoder
Frame Detector for SAV/EAV
1:20 DeMUX.
Timing and Alignment Jitter in accor-
dance with SMPTE292.
A Frame Alignment circuit detects the
EAV/SAV framing pattern and aligns data
at the 20 bit output port. The frame align-
ment can be disabled to allow other
coding schemes.
High-speed data input and output use
Loop-through bondings to reduce
reflections.
The Clock and Data Recovery Circuit
consists of:
a Bang-Bang Phase Detector (PD)
with data re-timing
Phase-Frequency Comparator (PFC),
a Lock Detect Circuit (LCD)
with Lock Alarm Output,
Complete Clock/20 (Data Recovery)
and Lock Acquisition on one IC.
The high-speed data input is differential
and compatible with PECL levels. It is
connected via loop-through transmission
lines to minimize stub related reflections.
For repeater applications a re-timed 75 S
cable driver output is provided, which
also can be used to drive an optical
module.
Digitally controlled capture and lock.
a Tristatable Charge Pump
a wide tuning range VCO.
–
Full capture range with true
Phase/Frequency detect between
VCO-CLK and REFCK.
The VCO centre frequency is determined
by the REFCK multiplied by 20. The loop
filter time constant is determined by an
external RC filter.
–
–
–
Bang-Bang Phase Detector be-
tween VCO-CLK and DATA.
Lock in range ±500 ppm or
±2000 ppm referred to REFCK.
Lock Alarm Output.
The GD14516A is packaged in a 68 pin
leaded Multi Layer Ceramic (MLC) pack-
age with cavity down for easy cooling.
When in lock, the digital Lock Detect Cir-
cuit uses the incoming data to control the
PLL. When not in lock, i.e. the VCO fre-
End of Active Video (EAV) / Start of
Active Video (SAV) detection and
alignment of the parallel 20 bit output
VCC_DMX VCC_CDR
CIP
VEE V3V3 V3V3A
Re-timed differential 75 Ω cable
driver output with external termination
resistors.
SOP
SON
SIP
SIN
Supply operation: 5 V and 3.3 V.
Power dissipation: 2500 mW typ.
NEN
SEN
PAR
DEN
TCKEN
TCK
TCKN
DOUT0
DI
DO
U
NRZI
&
Scrambler
Bang
Bang
Phase
Detector
VCO
Power down modes for repeater
applications.
DeMUX
Div.
/4
D
VCTL
DOUT19
68 pin Multi Layer Ceramic (MLC)
leaded package with transmission
lines.
Frame
Align.
FP
FFIN
Charge
Pump
/20
Clock
Divide
V
U
D
Lock
Detect
4:2
MUX
PFC
OUTCHP
U
D
R
SEL0
SEL1
REFCK
Applications
LOCK
REFCKN
Phase
Ctrl
CKOUT
HDTV studio equipment.
CPH0/1
VCCA VCCD VCCO