Datasheet > EBD11RD8ADFA

EBD11RD8ADFA

更新时间： 2022-12-21 03:19:10

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
19页	160K
描述
1GB Registered DDR SDRAM DIMM

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EBD11RD8ADFA 数据手册

PRELIMINARY DATA SHEET

1GB Registered DDR SDRAM DIMM

EBD11RD8ADFA (128M words × 72 bits, 2 Ranks)

Description

Features

The EBD11RD8ADFA is a 128M words × 72 bits, 2

• 184-pin socket type dual in line memory module

(DIMM)

ranks Double Data Rate (DDR) SDRAM Module,

mounting 18 pieces of DDR SDRAM sealed in TSOP

package. Read and write operations are performed at

the cross points of the CK and the /CK. This high-

speed data transfer is realized by the 2-bit prefetch-

pipelined architecture. Data strobe (DQS) both for read

and write are available for high speed and reliable data

bus design. By setting extended mode register, the on-

chip Delay Locked Loop (DLL) can be set enable or

disable. This module provides high density mounting

without utilizing surface mount technology. Decoupling

capacitors are mounted beside each TSOP on the

module board.

PCB height: 30.48mm

Lead pitch: 1.27mm

• 2.5V power supply

• Data rate: 333Mbps/266Mbps (max.)

• 2.5 V (SSTL_2 compatible) I/O

• Double Data Rate architecture; two data transfers per

clock cycle

• Bi-directional, data strobe (DQS) is transmitted

/received with data, to be used in capturing data at

the receiver

• Data inputs and outputs are synchronized with DQS

• 4 internal banks for concurrent operation

(Component)

• DQS is edge aligned with data for READs; center

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge; data

referenced to both edges of DQS

• Data mask (DM) for write data

• Auto precharge option for each burst access

• Programmable burst length: 2, 4, 8

• Programmable /CAS latency (CL): 2, 2.5

• Refresh cycles: (8192 refresh cycles /64ms)

7.8µs maximum average periodic refresh interval

• 2 variations of refresh

Auto refresh

Self refresh

• 1 piece of PLL clock driver, 2 piece of register driver

and 1 piece of serial EEPROM (2k bits EEPROM) for

Presence Detect (PD)

Document No. E0441E10 (Ver. 1.0)

Date Published December 2003 (K) Japan

URL: http://www.elpida.com

Elpida Memory,Inc. 2003

12 3 4 5 6 7...19

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