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DP83222 PDF预览

DP83222

更新时间: 2024-01-03 00:32:17
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
12页 180K
描述
CYCLONE Twisted Pair FDDI Stream Cipher Device

DP83222 技术参数

生命周期:Obsolete包装说明:QCCJ,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84JESD-30 代码:S-PQCC-J28
长度:11.43 mm功能数量:1
端子数量:28最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER认证状态:Not Qualified
座面最大高度:4.57 mm最大压摆率:200 mA
标称供电电压:5 V表面贴装:YES
电信集成电路类型:TELECOM CIRCUIT温度等级:COMMERCIAL
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD宽度:11.43 mm

DP83222 数据手册

 浏览型号DP83222的Datasheet PDF文件第2页浏览型号DP83222的Datasheet PDF文件第3页浏览型号DP83222的Datasheet PDF文件第4页浏览型号DP83222的Datasheet PDF文件第5页浏览型号DP83222的Datasheet PDF文件第6页浏览型号DP83222的Datasheet PDF文件第7页 
August 1994  
DP83222  
CYCLONETM Twisted Pair FDDI Stream Cipher Device  
General Description  
Features  
Y
Enables 100 Mbps FDDI signalling over Category  
Unshielded Twisted Pair (UTP) cable and Type  
Shielded Twisted Pair (STP)  
5
1
The DP83222 CYCLONE Stream Cipher Scrambler/  
Descrambler Device is an integrated circuit designed to in-  
terface directly with the serial bit streams of a Twisted Pair  
FDDI PMD. The DP83222 is designed to be fully compatible  
with the National Semiconductor FDDI Chip Sets, including  
the DP83223 TWISTERTM (Twisted Pair Transceiver). The  
DP83222 requires a 125 MHz Transmit Clock and corre-  
sponding Receive Clock for synchronous data scrambling  
and descrambling. The DP83222 is compliant with the ANSI  
X3T9.5 TP-PMD draft standard and is required for the re-  
duction of EMI emission over unshielded media. The  
DP83222 is specified to work in conjunction with existing  
twisted pair transceiver signalling schemes such as MLT-3  
or NRZI and enables high bandwidth transmission over  
Twisted Pair copper media.  
Y
Reduces EMI emissions over Twisted Pair media  
Y
Compatible with ANSI X3T9.5 TP-PMD Standard  
a
Y
Requires a single 5V supply  
Y
Y
Y
Y
Transparent mode of operation  
Flexible NRZ and NRZI format options  
Advanced BiCMOS process  
Signal Detect and Clock Detect inputs provided for en-  
hanced functionality  
Y
Suitable for Fiber Optic PMD replacement applications  
Block Diagram  
TL/F/11885–1  
FIGURE 1. DP83222 Block Diagram  
TM  
CYCLONETM, CDDTM, CDLTM, PLAYERTM, PLAYER  
and TWISTERTM are trademarks of National Semiconductor Corporation.  
a
C
1995 National Semiconductor Corporation  
TL/F/11885  
RRD-B30M105/Printed in U. S. A.  

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