Datasheet > CY8CPLC20-OCD

CY8CPLC20-OCD

更新时间： 2022-12-18 08:07:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		通信
页数	文件大小	规格书
44页	1404K
描述
Powerline Communication Solution

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数据手册

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CY8CPLC20-OCD 数据手册

CY8CPLC20

Powerline Communication Solution

■ Flexible On-Chip Memory

❐ 32 KB Flash Program Storage 50,000 Erase or Write Cycles

❐ 2 KB SRAM Data Storage

❐ EEPROM Emulation in Flash

■ Programmable Pin Configurations

❐ 25 mA Sink, 10 mA Source on all GPIO

❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive

Modes on all GPIO

❐ Up to 12 Analog Inputs on GPIO

❐ Configurable Interrupt on all GPIO

Features

■ Powerline Communication Solution

❐ Integrated Powerline Modem PHY

❐ Frequency Shift Keying Modulation

❐ Configurable baud rates up to 2400 bps

❐ Powerline Optimized Network Protocol

❐ Integrates Data Link, Transport, and Network Layers

❐ Supports Bidirectional Half Duplex Communication

❐ 8-bit CRC Error Detection to Minimize Data Loss

❐ I²C enabled Powerline Application Layer

❐ Supports I²C Frequencies of 50, 100, and 400 kHz

■ Additional System Resources

❐ I²C Slave, Master, and Multi-Master to 400 kHz

❐ Watchdog and Sleep Timers

❐ Reference Designs for 110V/240V AC and 12V/24V AC/DC

Powerlines

❐ User-Configurable Low Voltage Detection

❐ Integrated Supervisory Circuit

❐ Reference Designs comply with CENELEC EN

50065-1:2001 and FCC Part 15

❐ On-Chip Precision Voltage Reference

■ Powerful Harvard Architecture Processor

❐ M8C Processor Speeds to 24 MHz

❐ Two 8x8 Multiply, 32-Bit Accumulate

■ Programmable System Resources (PSoC^®Blocks)

❐ 12 Rail-to-Rail Analog PSoC Blocks provide:

• Up to 14-Bit ADCs

■ Complete Development Tools

❐ Free Development Software (PSoC Designer™)

❐ Full Featured In-Circuit Emulator (ICE) and Programmer

❐ Full Speed Emulation

❐ Complex Breakpoint Structure

❐ 128 KB Trace Memory

• Up to 9-Bit DACs

❐ Complex Events

❐ C Compilers, Assembler, and Linker

• Programmable Gain Amplifiers

• Programmable Filters and Comparators

❐ 16 Digital PSoC Blocks provide:

• 8 to 32-Bit Timers, Counters, and PWMs

• CRC and PRS Modules

• Up to Four Full Duplex UARTs

• Multiple SPI^TMMasters or Slaves

• Connectable to all GPIO Pins

❐ Complex Peripherals by Combining Blocks

Logic Block Diagram

Powerline Communication Solution

Embedded Application

Powerline Network

Programmable

Protocol

System Resources

Digital and Analog

Peripherals

Additional System

Physical Layer FSK

Modem

Resources

MAC, Decimator, I2C,

SPI, UART etc.

PLC Core

PSoC Core

Powerline Transceiver Packet

AC/DC Powerline Coupling Circuit

(110V/240V AC, 12V/24V AC/DC etc.)

Powerline

Cypress Semiconductor Corporation

Document Number: 001-48325 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised October 05, 2009

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