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CY7C09169AV-12AC PDF预览

CY7C09169AV-12AC

更新时间: 2024-02-08 20:25:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
17页 320K
描述
3.3V 8K/16K x 9 Synchronous Dual Port Static RAM

CY7C09169AV-12AC 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFP包装说明:PLASTIC, LEAD FREE, TQFP-100
针数:100Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.8Is Samacsys:N
最长访问时间:25 ns其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTURE
最大时钟频率 (fCLK):50 MHzI/O 类型:COMMON
JESD-30 代码:S-PQFP-G100JESD-609代码:e3
长度:14 mm内存密度:147456 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:9
湿度敏感等级:3功能数量:1
端口数量:2端子数量:100
字数:16384 words字数代码:16000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:16KX9
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP100,.63SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.0005 A
最小待机电流:3 V子类别:SRAMs
最大压摆率:0.25 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:14 mmBase Number Matches:1

CY7C09169AV-12AC 数据手册

 浏览型号CY7C09169AV-12AC的Datasheet PDF文件第2页浏览型号CY7C09169AV-12AC的Datasheet PDF文件第3页浏览型号CY7C09169AV-12AC的Datasheet PDF文件第4页浏览型号CY7C09169AV-12AC的Datasheet PDF文件第5页浏览型号CY7C09169AV-12AC的Datasheet PDF文件第6页浏览型号CY7C09169AV-12AC的Datasheet PDF文件第7页 
25/0251  
CY7C09159AV  
CY7C09169AV  
3.3V 8K/16K x 9  
Synchronous Dual Port Static RAM  
• High-speed clock to data access 9 and 12 ns (max.)  
• 3.3V Low operating power  
Features  
• True Dual-Ported memory cells which allow simulta-  
neous access of the same memory location  
Active = 135 mA (typical)  
Standby = 10 µA (typical)  
• Two Flow-Through/Pipelined devices  
— 8K x 9 organization (CY7C09159AV)  
— 16K x 9 organization (CY7C09169AV)  
• Three Modes  
• Fully synchronous interface for easier operation  
• Burst counters increment addresses internally  
Shorten cycle times  
Minimize bus noise  
— Flow-Through  
Supported in Flow-Through and Pipelined modes  
• Dual Chip Enables for easy depth expansion  
• Automatic power-down  
— Pipelined  
— Burst  
• Pipelinedoutputmodeonbothportsallowsfast83-MHz  
operation  
• Commercial and industrial temperature ranges  
Available in 100-pin TQFP  
• 0.35-micron CMOS for optimum speed/power  
v
Logic Block Diagram  
R/WL  
OEL  
R/WR  
OER  
CE0L  
CE1L  
CE0R  
CE1R  
1
1
0
0
0/1  
0/1  
1
0
0
1
0/1  
0/1  
FT/PipeL  
FT/PipeR  
9
9
I/O0LI/O8L  
I/O0RI/O8R  
I/O  
I/O  
Control  
Control  
13/14  
13/14  
[1]  
[1]  
A0A12/13L  
A0A12/13R  
Counter/  
Address  
Register  
Decode  
Counter/  
Address  
Register  
Decode  
CLKL  
CLKR  
ADSR  
True Dual-Ported  
RAM Array  
ADSL  
CNTENL  
CNTRSTL  
CNTENR  
CNTRSTR  
Notes:  
1. A0A12 for 8K; A0A13 for 16K.  
For the most recent information, visit the Cypress web site at www.cypress.com  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-06053 Rev. **  
Revised September 21, 2001  

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