Datasheet > C9850AT

C9850AT

更新时间： 2023-03-15 00:00:00

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		光电二极管
页数	文件大小	规格书
19页	220K
描述
Processor Specific Clock Generator, 200MHz, CMOS, PDSO56, TSSOP-56

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C9850AT 数据手册

ADVANCED INFORMATION

C9850

High Performance Pentium III Clock Generator

Product Features

Product Description

This device is an advanced performance single

package clock solution for high end Pentium III designs

using Rambus memory system architectures. It

provides all of the system motherboard’s clocks

needed to support the CPU, memory and peripheral

devices. Included in the frequency table are specific

+5% margin test frequencies to assist designers in

verification of adequate timing margins in designs. All

CPU (Host) clocks are deferential and comply with Intel

specified timing requirements.

•

Four differential host clocks

Two 3V Mref single ended for DRCG

Four 3V, 66 MHz clocks

Ten 3V, 33 MHz PCI clocks

Two 48 MHz clocks

Two 14.318 MHz reference clocks

Select logic for Differential Swing Control, Test

mode, Hi-Z, Power-down, Spread spectrum, and

frequency selection

External resistor for CPU current reference

56 Pin SSOP and TSSOP Package

•

Frequency Selection Table

SEL 100/133 SELA SELB

CPU(1:4),

CPU# (1:4)

100 MHz

105 MHz

200 MHz

High Z

3VMRef/

3VMRef_b

50 MHz

3V66

(0:3)

66.7 MHz

70.0 MHz

66.7 MHz

High Z

PCI (0:9)

48 M (0:1)

REF (1:2)

33.3 MHz

35.0 MHz

33.3 MHz

High Z

48 MHz

High Z

14.318 MHz

High Z

52.5 MHz

50 MHz

High Z

133.3 MHz

126.7 MHz

200 MHz

XIN/2

66.7 MHz

63.3 MHz

66.7 MHz

XIN/4

66.7 MHz

63.3 MHz

66.7 MHz

XIN/4

33.3 MHz

31.7 MHz

33.3 MHz

XIN/8

48 MHz

XIN/2

14.318 MHz

XIN

Block Diagram

Pin Configuration

VSSR

Ref1/MultSel0

Ref2/MultSel1

VDDR

VDDM

VDDR

3VMRef

3VMRef_b

VSSM

Spread#

CPU1

CPU1#

VDDC

CPU2

CPU2#

VSSC

CPU3

CPU3#

VDDC

CPU4

Sel1

Sel2

XIN

Ref1/MultSel0

OSC

XOUT

XIN

XOUT

VSSP

PCI0

PCI1

VDDP

PCI2

PCI3

VSSP

PCI4

PCI5

VDDP

PCI6

PCI7

VSSP

PCI8

Ref2/MultSel1

VSSR

3VMRef

3VMRef_b

I_REF

Spread#

VDDC

CPU(1:4)

VCO1

SEL100/133

PwrDwn#

CPU#(1:4)

CPU4#

VSSC

I_Ref

VDD

VSS

VSSC

VDDL

3V66(0:3)

VSSL

VDDP

PCI9

VDDP

VDD

3V66_0

3V66_1

VSS

PCI (0:9)

VSSP

SEL100/133

VSSU

48M0/SelA

48M1/SelB

VDDU

VSSL

VDDU

VCO2

3V66_2

3V66_3

VDDL

48M(0:1)/Sel(A:B)

VSSU

SELA/B

PwrDwn#

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07067 Rev. *A

12/22/2002

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