Very Low Power/Voltage CMOS SRAM
128K X 8 bit
BSI
BS62LV1025
DESCRIPTION
FEATURES
The BS62LV1025 is a high performance, very low power CMOS
Static Random Access Memory organized as 131,072 words by 8 bits
and operates from a wide range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.4uA and maximum access time of 55ns in 5V operation.
• Vcc operation voltage : 4.5V ~ 5.5V
• Very low power consumption :
Vcc = 5.0V C-grade : 35mA (Max.) operating current
I- grade : 40mA (Max.) operating current
0.4uA (Typ.) CMOS standby current
• High speed access time :
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
The BS62LV1025 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
-55
-70
55ns (Max.) at Vcc = 5.0V
70ns (Max.) at Vcc = 5.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
The BS62LV1025 is available in DICE form , JEDEC standard 32 pin
450mil Plastic SOP, 300mil Plastic SOJ , 600mil Plastic DIP, 8mmx
13.4mm STSOP and 8mmx20mm TSOP.
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2, CE1, and OE options
PRODUCT FAMILY
POWER DISSIPATION
SPEED
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
STANDBY
Operating
(ns)
PKG TYPE
(ICCSB1, Max)
(ICC, Max)
Vcc= 5.0V
Vcc=5.0V
Vcc=5.0V
BS62LV1025SC
BS62LV1025TC
BS62LV1025STC
BS62LV1025PC
BS62LV1025JC
BS62LV1025DC
BS62LV1025SI
BS62LV1025TI
BS62LV1025STI
BS62LV1025PI
BS62LV1025JI
BS62LV1025DI
SOP-32
TSOP-32
STSOP-32
PDIP-32
SOJ-32
DICE
SOP-32
TSOP-32
STSOP-32
PDIP-32
SOJ-32
DICE
+0 O C to +70 O
C
C
4.5V ~ 5.5V
4.5V ~ 5.5V
55 / 70
55 / 70
3.0uA
35mA
-40 O C to +85 O
5.0uA
40mA
PIN CONFIGURATIONS
BLOCK DIAGRAM
NC
A16
A14
A12
A7
1
VCC
A15
CE2
WE
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
A6
A7
A12
A14
A16
A15
A13
A8
3
4
5
A13
A8
Address
Memory Array
20
1024
A6
6
BS62LV1025SC
BS62LV1025SI
BS62LV1025PC
BS62LV1025PI
BS62LV1025JC
BS62LV1025JI
Row
Input
A5
7
A9
A4
1024 x 1024
8
A11
OE
Decoder
Buffer
A3
9
A2
10
11
12
13
14
15
16
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
A9
A11
A1
A0
DQ0
DQ1
DQ2
GND
1024
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
8
Column I/O
Write Driver
Sense Amp
8
8
Data
Output
Buffer
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
OE
128
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
Column Decoder
14
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
CE2
CE1
WE
Control
BS62LV1025TC
Address Input Buffer
9
BS62LV1025STC
BS62LV1025TI
BS62LV1025STI
10
11
12
13
14
15
16
OE
Vdd
Gnd
A5 A4 A3 A2 A1 A0 A10
A6
A5
A4
A1
A2
A3
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Revision 2.3
Jan. 2004
R0201-BS62LV1025
1
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