Datasheet > AZP94_1205

AZP94_1205

更新时间： 2022-06-02 18:30:20

品牌	Logo	应用领域
AZM		时钟发生器
页数	文件大小	规格书
9页	545K
描述
PECL/ECL Ã·1, Ã·2 Clock Generation Chip with Tristate Compatible Outputs

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数据手册

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AZP94_1205 数据手册

AZP94

PECL/ECL ÷1, ÷2 Clock Generation

Chip with Tristate Compatible Outputs

www.azmicrotek.com

FEATURES

DESCRIPTION

• Selectable Divide Ratio

• Selectable Enable Polarity and

Threshold (CMOS or PECL)

• Tristate Compatible Outputs

• Input Buffer Powers Down

when Disabled

The AZP94 is a ÷1 or ÷2 clock generation part specifically designed to

accommodate Colpitts or Pierce based oscillators. The tristate compatible

outputs allow for on-the-fly switching of multiple oscillators on a common

bus. Other features are incorporated to reduce board components. A voltage

reference and input biasing allows for easy oscillator interface.

The AZP94 provides a ÷ 2 mode of operation for more frequency options

and is selectable with a single connection. A selectable enable is also

provided which doubles as a reset when the AZP94 is in ÷2 mode. With a

single connection, the enable can be selected to operate as active high or

active low.

• High Bandwidth

1.5+ GHz (÷1)

3.0+ GHz (÷2)

• -145 dBc/Hz (÷1) Typical

Noise Floor

•

-151 dBc/Hz (÷2) Typical

Noise Floor

BLOCK DIAGRAM

APPLICATIONS

• Colpitts or Pierce based

oscillators

• Multiple oscillators on a

common bus

PACKAGE AVAILABILITY

•

MLP8

Green/RoHS Compliant/Pb-Free

Part Number (PN)

Package

Marking

J4G <Date Code>²

AZP94NAG¹

MLP8

Tape & Reel - Add 'R1' at end of PN for 7in (1k parts), 'R2' (2.5k) for 13in

See www.azmicrotek.com for date code format

www.azmicrotek.com

+1-480-962-5881

1630 S Stapley Dr, Suite 127

Mesa, AZ 85204 USA

Request a Sample

May 2012, Rev 2.0

12 3 4 5 6 7...9

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