Programmable Frequency Sweep and
Output Burst Waveform Generator
Preliminary Technical Data
AD5930
FEATURES
GENERAL DESCRIPTION
Programmable frequency profile—no external
components necessary
Ouput frequency up to 25 Mhz
Burst and listen capability
Predefined frequency profile minimizes number
of DSP/µcontroller writes
Sinusoidal/triangular/square wave outputs
Automatic or single pin control of frequency stepping
Frequency starts at known phase—increments at 0° phase
or phase continuous
The AD59301 is a waveform generator with programmable
frequency sweep and output burst capability. Utilizing
embedded digital processing allowing enhanced frequency
control the device generates synthesized analog or digital
frequency-stepped waveforms. Because frequency profiles are
preprogrammed continuous write cycles are eliminated, thereby
freeing up valuable DSP/µController resources. Waveforms start
from a known phase and are incremented phase conti0nuously
allowing phase shifts to be easily determined. Consuming only
8mA the AD5930 provides a convenient low power solution to
waveform generation.
Powerdown mode (20 µA)
+2.3 V to +5.5 V power supply
Extended temperature range −40°C to +105°C
20-lead TSSOP
The AD5930 can be operated in three modes. In continuous
output mode the device outputs the required frequency for a
defined length of time and then steps to the next frequency.
The length of time the device outputs a particular frequency
can be either preprogrammed and the device increments the
frequency automatically or alternatively can be incremented
externally via the CTRL pin. In Burst mode, the device outputs
it’s frequency for a length of time and then returns to midscale
for a further predefined length of time before stepping to the
next frequency. In MSB mode a digital output is generated.
APPLICATIONS
Frequency Sweeping/Radar
Network/Impedance Measurements
Incremental Frequency stimulus
Sensory Applications—Proximity and Motion
BFSK
Frequency Bursting/Pulse Trains
(continued on Page 3)
1 Protected by US Patent Number 6747583, other patents pending.
FUNCTIONAL BLOCK DIAGRAM
INTERRUPT STANDBY
DVDD CAP/2.6V
DGND
AGND AVDD
REGULATOR
VCC
2.5V
SYNC
SYNC OUT
MCLK
CTRL
BUFFER
BUFFER
OUTPUT BURST
CONTROLLER
OPDGND
MSB OUT
DATA
SYNC
INCREMENT
CONTROLLER
24-BIT
PIPELINED
DOS CORE
IOUT
IOUT
10-BIT
DAC
DATA
INCR
FREQUENCY
CONTROLLER
24
DATA
AND CONTROL
ON-BOARD
REFERENCE
FULL-SCALE
CONTROL
COMP
CONTROL
REGISTER
SERIAL INTERFACE
REF
FS ADJUST
FSYNC SCLK SDATA
Figure 1.
Rev. PrF
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