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AD5310R

更新时间: 2023-12-20 18:45:17
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
24页 529K
描述
10位nanoDAC、SPI接口以及2 ppm/°C 片内基准电压源

AD5310R 数据手册

 浏览型号AD5310R的Datasheet PDF文件第2页浏览型号AD5310R的Datasheet PDF文件第3页浏览型号AD5310R的Datasheet PDF文件第4页浏览型号AD5310R的Datasheet PDF文件第5页浏览型号AD5310R的Datasheet PDF文件第6页浏览型号AD5310R的Datasheet PDF文件第7页 
10-Bit nanoDAC with SPI/I2C Interface  
and 2 ppm/°C On-Chip Reference  
Data Sheet  
AD5310R/AD5311R  
FEATURES  
FUNCTIONAL BLOCK DIAGRAMS  
V
V
V
DD  
LOGIC  
REF  
High relative accuracy (INL): 0.5 LSB maximum  
Low drift 2.5 V reference: 2 ppm/°C typical  
Selectable span output: 2.5 V or 5 V  
Total unadjusted error (TUE): 0.06% of FSR maximum  
Offset error: 1.5 mV maximum  
POWER-ON  
RESET  
AD5310R  
2.5V  
REF  
LDAC  
REF  
10-BIT  
DAC  
REGISTER  
OUTPUT  
BUFFER  
V
OUT  
DAC  
RESET  
Gain error: 0.05% of FSR maximum  
Low glitch: 0.1 nV-sec  
High drive capability: 20 mA  
Low power: 1.2 mW at 3.3 V  
INPUT  
CONTROL LOGIC  
POWER-DOWN  
CONTROL LOGIC  
RESISTOR  
NETWORK  
Independent logic supply: 1.8 V logic compatible  
Wide operating temperature range: −40°C to +105°C  
Robust 4 kV HBM ESD protection  
SYNC  
SCLK SDI  
LOGIC  
GND  
Figure 1. AD5310R  
APPLICATIONS  
V
V
V
DD  
REF  
Process controls  
Data acquisition systems  
Digital gain and offset adjustment  
Programmable voltage sources  
Optical modules  
POWER-ON  
RESET  
AD5311R  
2.5V  
REF  
LDAC  
REF  
10-BIT  
DAC  
REGISTER  
OUTPUT  
BUFFER  
V
OUT  
DAC  
RESET  
INPUT  
CONTROL LOGIC  
POWER-DOWN  
CONTROL LOGIC  
GENERAL DESCRIPTION  
RESISTOR  
NETWORK  
The AD5310R/AD5311R, members of the nanoDAC® family, are  
low power, single-channel, 10-bit buffered voltage output DACs.  
The devices include an enabled by default internal 2.5 V  
reference, and provides 2 ppm/°C. The output span can be  
programmed to be 0 V to VREF or 0 V to 2 × VREF. All devices  
operate from a single 2.7 V to 5.5 V supply and are guaranteed  
monotonic by design. The devices are available in 10-lead  
MSOP packages.  
SDA  
SCL  
A0  
GND  
Figure 2. AD5311R  
Table 1. Related Devices  
Interface  
Reference  
12-Bit  
10-Bit  
AD53101  
AD53111  
SPI  
I2C  
External  
External  
AD5681R  
The internal power-on reset circuit of the AD5310R/AD5311R  
ensures that the DAC register is written to zero scale at powerup  
when the internal output buffer is configured in normal mode.  
The devices contain a power-down mode that reduces the  
current consumption of the device to 2 µA at 5 V.  
1 The AD5310R and AD5311R are not pin-to-pin or software compatible with  
the AD5310 and AD5311, respectively.  
PRODUCT HIGHLIGHTS  
The AD5310R/AD5311R use a versatile SPI or I2C interface,  
1. High Relative Accuracy (INL): 0.5 LSB maximum.  
2. Low Drift 2.5 V On-Chip Reference: 5 ppm/°C maximum  
temperature coefficient.  
RESET  
including an asynchronous  
pin and a VLOGIC pin that  
provides 1.8 V compatibility.  
Rev. B  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 ©2014–2017 Analog Devices, Inc. All rights reserved.  
Technical Support  
www.analog.com  
 
 
 
 
 

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