TSS902E
Viterbi and Reed–Solomon FEC Decoder
1. Description
Digital communication channels are inherently noisy,
making transmission error control essential for reliable
communication at low transmit power.
decoder (k=7) and
controller.
The convolutional deinterleaver, l=12 bytes for RS
(204, 188, T=8) configuration.
The outer decoder performs the second level error
protection, using a Reed Solomon (255, 239) error
correcting process.
The descrambler for energy dispersal removal.
A micro–processor interface to setup the device and
monitor the testability functions.
a
synchronization/clock
G
G
The TEMIC TSS902E is a single–chip Forward Error
Correction decoder; it conforms to the MPEG–II
transport layer protocol specified by ISO/IEC standard
and FEC requirements of Digital Video Broadcasting
(DVB) specification; its typical applications are DVB
satellites, regenerative multi–media transmission
satellites and military communications.
G
G
While monitoring the inner Viterbi decoder BER output,
the phase and the depuncturing pattern are tuned until
the Viterbi decoder proper alignment is found.
The TEMIC TSS902E capabilities rely on Viterbi and
Reed–Solomon decoding algorithms to achieve
extremely low bit–error rate (BER) on the transmitted
data. Allowing discontinuous data blocks transmission,
the TSS902E burst mode feature is unique.
The Viterbi decoder output feeds the deinterleaver and
Reed–Solomon decoder synchronization module. Once
the synchronization words have been found, the
deinterleaver, the outer Reed–Solomon decoder and the
descrambler are properly aligned.
The component is made of the following blocks:
G
The inner decoder which performs the first level
error detection and correction.
Each functional block may be by–passed, giving more
flexibility to a system designer.
This unit is made of a depuncturing block, a Viterbi
2. Features
2.1. General
2.3. Synchronization controller
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Compliant with ETS 300 421 for DVB, DVB–S.
Compliant with ISO/IEC–CD 13818–1 MPEG–II
transport layer protocol.
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Automatic synchronization capabilities for QPSK or
BPSK.
Responds to inverted synchronization byte.
Programmable synchronization byte.
G
G
G
G
G
G
G
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Input code rate frequency up to 10 MBits/sec at 5V.
On–chip Bit Error Rate monitoring.
G
2
SEU immunity better than 30 MeV/mg/cm
2.4. Convolutional deinterleaver
Total dose better than 50 Krad (Si).
Supply voltage 3 to 5V.
Power consumption 1W at 5V / 10MHz external
clock frequency (code rate 7/8).
0.6 µm drawn CMOS, 3 metal layers.
132–pin MQFP.
G
Error protected frame length n = 204.
Interleave depth I = 12.
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G
2.5. Reed Solomon Decoder
G
G
G
Supported programmable shortened code length
K = 34 to 239, T = 8.
Correction capability up to T = 8 bytes.
2.2. Viterbi Decoder
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1
2
3
5
7
Selectable code rates / , / , / , / and /
2 3 4 6 8
or automatic acquisition mode.
2.6. Descrambler (Energy Dispersal)
G
G
G
Hard decision or 3–Bit soft–decision decoder inputs.
Constraint length k = 7.
15
14
G
Polynomial generator q(x) = X + X + 1.
MPEG–II inverted synchronization byte.
–4
1
E /N for BER 2.10 (code rate / ) 3.5 dB.
G
b
0
2
MHS
Rev. D – April 1999
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