Datasheet > STM32H743

STM32H743

更新时间： 2022-10-12 15:51:48

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		/
页数	文件大小	规格书
357页	4834K
描述
32-bit ArmÂ® CortexÂ®-M7 480MHz MCUs, up to 2MB Flash, up to 1MB RAM, 46 com. and analog interfaces

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STM32H743 数据手册

STM32H742xI/G STM32H743xI/G

32-bit Arm^®Cortex^®-M7 480MHz MCUs, up to 2MB Flash,

up to 1MB RAM, 46 com. and analog interfaces

Datasheet - production data

Features

FBGA

Core

• 32-bit Arm Cortex -M7 core with double-

precision FPU and L1 cache: 16 Kbytes of data

and 16 Kbytes of instruction cache; frequency

up to 480 MHz, MPU, 1027 DMIPS/

2.14 DMIPS/MHz (Dhrystone 2.1), and DSP

instructions

LQFP100

(14 x 14 mm)

LQFP144

(20 x 20 mm)

LQFP176

(24 x 24 mm)

LQFP208

(28 x 28 mm)

TFBGA100

(8 x 8 mm)

TFBGA240+25

(14 x 14 mm)

UFBGA169

(7 x 7 mm)

UFBGA176+25

(10 x 10 mm)

(1)

Memories

• 1.62 to 3.6 V application supply and I/Os

• POR, PDR, PVD and BOR

• Up to 2 Mbytes of Flash memory with read-

while-write support

• Dedicated USB power embedding a 3.3 V

• Up to 1 Mbyte of RAM: 192 Kbytes of TCM

RAM (inc. 64 Kbytes of ITCM RAM +

internal regulator to supply the internal PHYs

128 Kbytes of DTCM RAM for time critical

routines), Up to 864 Kbytes of user SRAM, and

4 Kbytes of SRAM in Backup domain

• Embedded regulator (LDO) with configurable

scalable output to supply the digital circuitry

• Voltage scaling in Run and Stop mode (6

• Dual mode Quad-SPI memory interface

configurable ranges)

running up to 133 MHz

• Backup regulator (~0.9 V)

• Flexible external memory controller with up to

32-bit data bus: SRAM, PSRAM,

• Voltage reference for analog peripheral/V

REF+

• Low-power modes: Sleep, Stop, Standby and

SDRAM/LPSDR SDRAM, NOR/NAND Flash

memory clocked up to 100 MHz in

Synchronous mode

supporting battery charging

BAT

Low-power consumption

• CRC calculation unit

• V

battery operating mode with charging

capability

BAT

Security

• CPU and domain power state monitoring pins

• ROP, PC-ROP, active tamper

• 2.95 µAin Standby mode (Backup SRAM OFF,

General-purpose input/outputs

RTC/LSE ON)

• Up to 168 I/O ports with interrupt capability

Clock management

Reset and power management

• Internal oscillators: 64 MHz HSI, 48 MHz

HSI48, 4 MHz CSI, 32 kHz LSI

• 3 separate power domains which can be

independently clock-gated or switched off:

• External oscillators: 4-48 MHz HSE,

– D1: high-performance capabilities

32.768 kHz LSE

– D2: communication peripherals and timers

– D3: reset/clock control/power management

• 3× PLLs (1 for the system clock, 2 for kernel

clocks) with Fractional mode

April 2019

DS12110 Rev 7

1/357

This is information on a product in full production.

www.st.com

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