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MU9C8328 PDF预览

MU9C8328

更新时间: 2024-01-10 01:43:07
品牌 Logo 应用领域
MUSIC 以太网
页数 文件大小 规格书
16页 97K
描述
Ethernet Interface

MU9C8328 技术参数

是否Rohs认证: 不符合生命周期:Contact Manufacturer
零件包装代码:QFP包装说明:QFP,
针数:100Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.89
Is Samacsys:NJESD-30 代码:R-PQFP-G100
JESD-609代码:e0湿度敏感等级:3
功能数量:1端子数量:100
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装形状:RECTANGULAR封装形式:FLATPACK
认证状态:Not Qualified标称供电电压:5 V
表面贴装:YES电信集成电路类型:INTERFACE CIRCUIT
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子位置:QUAD
Base Number Matches:1

MU9C8328 数据手册

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Preliminary Data Sheet  
MU9C8328 Ethernet Interface  
APPLICATION BENEFITS  
GENERAL DESCRIPTION  
The MU9C8328 speeds up bridging operations using  
Ethernet controller chips with serial NRZ data outputs,  
such as AMD’s MACE™, National’s SONIC™, and  
Motorola’s QUICC™ controllers, by parsing the Ethernet  
frame independently of the Ethernet controller device, and  
notifying it whether to accept or reject the incoming frame.  
The MU9C8328 supports both positive and negative  
filtering on the Destination address and learning of new  
Source addresses, by efficiently controlling the compare  
activities of the MUSIC LANCAM Family. Filtering and  
learning routines are user configurable. These routines  
are automatically invoked by the internal state machine  
based on the contents of the incoming frame and the  
configuration settings. For aging and other housekeeping  
routines, the MU9C8328 provides the proper sequencing  
and timing of LANCAM accesses for an external  
processor.  
Ø Single port 10 MHz Ethernet address parsing,  
filtering, and learning state machine at wire  
speed  
Ø Glue-free interface between the MUSIC  
LANCAM® Family and AMD, National,  
Motorola, or similar Ethernet Controllers  
having an NRZ serial data port  
Ø Selectable filtering and learning decisions  
on DA and SA compares  
Ø Supports cascaded MUSIC LANCAM series  
for long station lists  
Ø Host processor port for LANCAM  
initialization and housekeeping activities  
Ø Supports system clock rates from 20 MHz to  
33 MHz  
The MU9C8328 receives serial NRZ data from the  
Ethernet controller chip, finds the Start delimiter, and  
loads the DA and SA into registers. The DA is sent to the  
LANCAM for filtering and, depending on the filter action  
Ø 100-pin PQFP package  
Ø 5 Volt operation  
LA NC AM IN TER FA CE  
/C S  
/AS  
SERC L K  
/W E  
A(2-0)  
3
SERD AT  
/N ET RD Y  
/R EJ ECT  
STA TE  
M A CH IN E  
NETW OR K  
PRO CESS OR  
IN T ERFA C E  
IN T ERFA C E  
D(15-0)  
REA D Y  
/INT  
SYSC LK  
/R ESET  
CO NT RO L  
STAT US  
OP -C OD E  
ASS OC IAT ED D ATA  
Block Diagram  
MUSIC Semiconductors, the MUSIC logo, the phrase “MUSIC Semiconductors”, and LANCAM are registered trademarks of MUSIC  
Semiconductors. All other trademarks are registered by their respective owners. MUSIC is a trademark of MUSIC Semiconductors.  
11 February 1999 Rev. 4a  

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