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MT8976 PDF预览

MT8976

更新时间: 2024-02-11 03:21:19
品牌 Logo 应用领域
MITEL /
页数 文件大小 规格书
26页 340K
描述
ISO-CMOS ST-BUS⑩ FAMILY T1/ESF Framer Circuit

MT8976 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:QCCN, LCC44,.65SQReach Compliance Code:unknown
风险等级:5.92JESD-30 代码:S-XQCC-N44
JESD-609代码:e0端子数量:44
最高工作温度:70 °C最低工作温度:
封装主体材料:CERAMIC封装代码:QCCN
封装等效代码:LCC44,.65SQ封装形状:SQUARE
封装形式:CHIP CARRIER电源:5 V
认证状态:Not Qualified子类别:Digital Transmission Controllers
最大压摆率:15 mA标称供电电压:5 V
表面贴装:YES技术:CMOS
电信集成电路类型:FRAMER温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD

MT8976 数据手册

 浏览型号MT8976的Datasheet PDF文件第2页浏览型号MT8976的Datasheet PDF文件第3页浏览型号MT8976的Datasheet PDF文件第4页浏览型号MT8976的Datasheet PDF文件第5页浏览型号MT8976的Datasheet PDF文件第6页浏览型号MT8976的Datasheet PDF文件第7页 
MT8976  
ISO-CMOS ST-BUS FAMILY  
T1/ESF Framer Circuit  
ISSUE 9  
May 1995  
Features  
Ordering Information  
D3/D4 or ESF framing and SLC-96 compatible  
MT8976AC  
MT8976AE  
MT8976AP  
28 Pin Ceramic DIP  
28 Pin Plastic DIP  
44 Pin PLCC  
2 frame elastic buffer with 32 µsec jitter buffer  
Insertion and detection of A, B,C,D bits.  
Signalling freeze, optional debounce  
-40°C to 85°C  
Selectable B8ZS, jammed bit (ZCS) or no zero  
code suppression  
Yellow alarm and blue alarm signal capabilities  
Bipolar violation count, F error count, CRC  
T
Description  
error count  
Selectable robbed bit signalling  
Frame and superframe sync. signals, Tx and Rx  
AMI encoding and decoding  
The MT8976 is Mitel’s second generation T1  
interface solution. The MT8976 meets the Extended  
Super Frame format (ESF), the current D3/D4 format  
and is compatible with SLC-96 systems.  
Per channel, overall, and remote loop around  
Digital phase detector between T1 line & ST-  
BUS  
The MT8976 interfaces to DS1 1.544 Mbit/sec digital  
trunk.  
One uncommitted scan point and drive point  
Pin compatible with MT8977 and MT8979  
ST-BUS compatible  
Applications  
DS1/ESF digital trunk interfaces  
Computer to PBX interfaces (DMI and CPI)  
High speed computer to computer data links  
C1.5i  
TxSF  
RxFDLClk  
RxFDL  
ST-BUS  
Timing  
Circuitry  
C2i  
2 Frame  
Elastic Buffer  
with Slip  
F0i  
RxA  
RxSF  
Control  
Remote &  
Digital  
Loopbacks  
RxB  
TxA  
DS1  
Link  
Interface  
DSTo  
DSTi  
Data  
Interface  
TxB  
TxFDLClk  
TxFDL  
2048-1544  
Converter  
RxD  
CSTi0  
CSTi1  
CSTo  
Serial  
Control  
Interface  
E1.5i  
ABCD  
Signalling RAM  
E8Ko  
VSS  
DS1  
Counter  
Phase  
Detector  
XCtl  
XSt  
Control Logic  
VDD  
Figure 1 - Functional Block Diagram  
4-29  

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