Datasheet > MT48H16M32LF

MT48H16M32LF

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
镁光 - MICRON		动态存储器
页数	文件大小	规格书
73页	2407K
描述
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM

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数据手册

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MT48H16M32LF 数据手册

512Mb : 32 Me g x 16, 16 Me g x 32 Mo b ile SDRAM

Fe a t u re s

Mo b ile SDRAM

MT48H32M16LF – 8 Me g x 16 x 4 b a n ks

MT48H16M32LF/LG – 4 Me g x 32 x 4 b a n ks

Fe a t u re s

Op t io n s

Ma rkin g

• Endur-IC™ technology

• VDD/ VDDQ

• Fully synchronous; all signals registered on positive

edge of system clock

• VDD = 1.7–1.95V; VDDQ = 1.7–1.95V

• Internal, pipelined operation; column address can

be changed every clock cycle

• Four internal banks for concurrent operation

• Programmable burst lengths: 1, 2, 4, 8, and

continuous

• Auto precharge, includes concurrent auto precharge

• Auto refresh and self refresh modes

• LVTTL-compatible inputs and outputs

• On-chip temperature sensor to control refresh rate

• Partial-array self refresh (PASR)

– 1.8V/ 1.8V

• Row size option

– Standard addressing option

– Reduced page-size option

• Configuration

– 32 Meg x 16 (8 Meg x 16 x 4 banks)

– 16 Meg x 32 (4 Meg x 32 x 4 banks)

• Plastic “green” packages

– 54-Ball VFBGA (10mm x 11.5mm)

– 90-Ball VFBGA (10mm x 13mm)

• Timing – cycle time

– 7.5ns at CL = 3

3, 4

32M16

16M32

-75

-8

– 8ns at CL = 3

• Power

• Deep power-down (DPD)

• Selectable output drive (DS)

– Standard IDD2P/ IDD7

– Low IDD2P/ IDD7

• Operating temperature range

– Commercial (0°C to +70°C)

– Industrial (–40°C to +85°C)

• Design revision

None

Ta b le 1:

Co n fig u ra t io n Ad d re ssin g

None

JEDEC-

Re d u ce d

Pa g e -Size

Op t io n ²

DQ Bu s

Wid t h

St a n d a rd

Arch it e ct u re

Op t io n

Number of banks

Bank address balls

Row address balls

Column address balls

Row address balls

Column address balls

BA0, BA1

–

Notes: 1. For continuous page burst, contact factory

for availability.

BA0, BA1

A0–A12

A0–A9

x16

x32

2. For reduced page-size option, contact fac-

tory for availability.

3. LG is a reduced page-size option. Contact

factory for availability.

–

A0–A12

A0–A8

A0–A13

A0–A7

4. Only available for x32 configuration.

5. Only available for x16 configuration.

Ta b le 2:

Ke y Tim in g Pa ra m e t e rs

CL = CAS (READ) latency

Clo ck Ra t e (MHz)

Acce ss Tim e

Sp e e d

Gra d e

CL = 2

CL = 3

CL = 2

CL = 3

-75

-8

104

100

133

125

9ns

6ns

7ns

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03

MT48H32M16LF_1.fm - Rev. H 6/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

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