PRELIMINARY‡
256Mb: x4, x8, x16
DDR333 SDRAM Addendum
MT46V64M4 –16 Meg x 4 x 4 banks
MT46V32M8 – 8 Meg x 8 x 4 banks
MT46V16M16 – 4 Meg x 16 x 4 banks
DOUBLE DATA RATE
(DDR) SDRAM
For the latest data sheet revisions, please refer to the Micron
Website:www.micron.com/dramds
FEATURES
DDR333COMPATIBILITY
• 167 MHz Clock, 333 Mb/s/p data rate
• VDD = +2.5V ±±.2V, VDDQ = +2.5V ±±.2V
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two - one per byte)
DDR333 meets or surpasses all DDR266 timing re-
quirements thus assuring full backwards compatibility
with current DDR designs. In addition, these devices
t
support concurrent auto-precharge and RAS lockout
for improved timing performance. The 256Mb,
DDR333 device will support an (tREFI) average peri-
odic refresh interval of 7.8us.
The standard 66-pin TSOP package is offered for
point-to-point applications where the FBGA package
is intended for the multi-drop systems.
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has
two - one per byte)
The Micron 256Mb data sheet provides full specifi-
cations and functionality unless specified herein.
CONFIGURATION
• Programmable burst lengths: 2, 4, or 8
• Concurrent Auto Precharge option supported
• Auto Refresh and Self Refresh Modes
• FBGA package available
Architecture
64 Meg x 4
32 Meg x 8
16 Meg x 16
Configuration
16 Meg x 4 x 4 banks 8 Meg x 8 x 4 banks 4 Meg x 16 x 4 banks
RefreshCount
8K
8K
8K
RowAddressing
BankAddressing
ColumnAddressing
8K (A0–A12)
4(BA0,BA1)
2K (A0–A9, A11)
8K (A0–A12)
4(BA0,BA1)
1K (A0–A9)
8K (A0–A12)
4(BA0,BA1)
512(A0– A8)
• 2.5V I/O (SSTL_2 compatible)
t
• RAS lockout (tRAP = tRCD)
• Backwards compatible with DDR2±± and DDR266
OPTIONS
• Configuration
PART NUMBER
KEYTIMINGPARAMETERS3
64 Meg x 4 (16 Meg x 4 x 4 banks)
32 Meg x 8 (8 Meg x 8 x 4 banks)
16 Meg x 16 (4 Meg x 16 x 4 banks)
• Plastic Package
64M4
32M8
16M16
SPEED
GRADE CL = 21
CLOCKRATE
DATA-OUT ACCESS DQS-DQ
CL = 2.51 WINDOW2 WINDOW SKEW
-6
-6T
-75Z
133MHz 167MHz
133MHz 167MHz
133MHz 133MHz
2.15ns
2.0ns
2.5ns
0.70ns +0.35ns
0.75ns +0.45ns
0.75ns +0.50ns
66-Pin TSOP (OCPL)
6±-Ball FBGA (16x9mm)
• Timing - Cycle Time
TG
FJ
NOTE: 1. CL = CAS (Read) Latency
6ns @ CL = 2.5 (DDR333B–FBGA)1
6ns @ CL = 2.5 (DDR333B–TSOP)1
7.5ns @ CL = 2 (DDR266A)2
• Self Refresh
-6
-6T
-75Z
2. With a 50/50 clock duty cycle and a minimum clock
rate @ CL = 2 ( -75Z) and CL = 2.5 (-6, -6T).
3. -75, -8 are also available; see base data sheet.
Standard
none
NOTE: 1. Supports PC2700 modules with 2.5-3-3 timing
2. Supports PC2100 modules with 2-3-3 timing
256Mb: x4, x8, x16 DDR333 SDRAM
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2001,MicronTechnology,Inc.
1
‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRONWITHOUTNOTICE.PRODUCTSAREONLYWARRANTEDBYMICRONTOMEETMICRON’SPRODUCTIONANDDATASHEETSPECIFICATIONS.
5秒后页面跳转
MAX6675资料手册参数详解、引脚配置说明
LM258引脚图及功能介绍、主要参数分析
CD4052资料手册参数详解、引脚配置说明
一文带你了解TPS5430资料手册分析：参数介绍、引脚配置说明
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
