MT3170B/71B, MT3270B/71B, MT3370B/71B
Wide Dynamic Range DTMF Receiver
ISSUE 2
May 1995
Features
•
Wide dynamic range (50dB) DTMF Receiver
Ordering Information
•
Call progress (CP) detection via cadence
indication
MT3170/71BE
8 Pin Plastic DIP
8 Pin Plastic DIP
18 Pin SOIC
MT3270/71BE
MT3370/71BS
MT3370/71BN
•
•
•
•
•
4-bit synchronous serial data output
20 Pin SSOP
Software controlled guard time for MT3x70B
Internal guard time circuitry for MT3x71B
Powerdown option (MT317xB & MT337xB)
-40 °C to +85 °C
signalling. The MT3x70B provides an early steering
(ESt) logic output to indicate the detection of a DTMF
signal and requires external software guard time to
validate the DTMF digit. The MT3x71B, with preset
internal guard times, uses a delay steering (DStD)
logic output to indicate the detection of a valid DTMF
digit. The 4-bit DTMF binary digit can be clocked out
synchronously at the serial data (SD) output. The
SD pin is multiplexed with call progress detector
output. In the presence of supervisory tones, the
call progress detector circuit indicates the cadence
(i.e., envelope) of the tone burst. The cadence
information can then be processed by an external
microcontroller to identify specific call progress
signals. The MT327xB and MT337xB can be used
with a crystal or a ceramic resonator without
additional components. A power-down option is
provided for the MT317xB and MT337xB.
4.194304MHz crystal or ceramic resonator
(MT337xB and MT327xB)
•
•
External clock input (MT317xB)
Guarantees non-detection of spurious tones
Applications
•
•
•
Integrated telephone answering machine
End-to-end signalling
Fax Machines
Description
The MT3x7xB is a family of high performance DTMF
receivers which decode all 16 tone pairs into a 4-bit
binary code. These devices incorporate an AGC for
wide dynamic range and are suitable for end-to-end
➀
PWDN
Steering
Digital
Circuit
ESt
or
DStD
VDD
Guard
Voltage
Bias Circuit
➂
Time
High
Group
Filter
VSS
Parallel to
Serial
Converter
& Latch
ACK
Dial
Tone
Filter
Code
Converter
and
Anti-
alias
Filter
Digital
INPUT
AGC
Detector
Algorithm
Latch
Low
Group
Filter
Mux
SD
➁
Oscillator
OSC2
and
Clock
Circuit
Energy
Detection
OSC1
(CLK)
To All Chip Clocks
➀ MT3170B/71B and MT337xB only.
➁ MT3270B/71B and MT337xB only.
➂ MT3x71B only.
Figure 1 - Functional Block Diagram
4-3