Datasheet > EDI8L3265C

EDI8L3265C

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
WEDC		/
页数	文件大小	规格书
6页	559K
描述
64Kx32 CMOS High Speed

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EDI8L3265C 数据手册

EDI8L3265C

64Kx32 SRAM

Features

64Kx32CMOSHighSpeed

Static RAM

64Kx32 bit CMOS Static

The EDI8L3265C is a high speed, high performance, four

megabit density Static RAM organized as a 64Kx32 bit

array(

Random Access Memory Array

Fast Access Times: 12*, 15, 20, and 25ns

Individual Byte Selects

Four Byte Selects, two Chip Enables, Write Control, and

Output Enable provide the user with a flexible memory

solution( The user may independently enable each of the

four bytes, and, with minimal additional peripheral logic,

the unit may be configured as a 128Kx16 array(

Fully asynchronous circuitry is used, requiring no clocks or

refreshing for operation and providing equal access and

cycle times for ease of use(

User Configurable Organization

with Minimal Additional Logic

Master Output Enable and Write Control

TTL Compatible Inputs and Outputs

Fully Static, No Clocks

Surface Mount Package

The EDI8L3265C, allows 2 megabits of memory to be

placed in less than 0(990 square inches of board space(

The EDI8L3265C can be upgraded to 128K, 256K or

512Kx32 in the same footprint using the EDI8L32128,

EDI8L32256 or the EDI8L32512C( ꢀSee page 6 for up-

grade paths)(

68 Lead PLCC, No( 99 ꢀJEDEC-M0-47AE)

Small Footprint, 0(990 Sq( In(

Multiple Ground Pins for Maximum

Noise Immunity

Single +5V ꢀ±5%) Supply Operation

*AdvanceInformation

Note:SolderReflowtemperaturesshouldnotexceed260°Cfor10secondsꢀ

Pin Configurations and Block Diagram

PinNames

AØ-A15

EØ-E1

BSØ-BS3

Address Inputs

Chip Enables (one per word)

Byte Selects (One per Byte)

Master Write Enable

Master Output Enable

CommonDataInput/Output

Power (+5V±5%)

DQØ-DQ31

VCC

VSS

Ground

No Connection

Notes:1ꢀSeepage6forupgradepathsꢀ

March1997 Revꢀ4

ECO#8302

WhiteElectronicDesignsCorporation(602)437-1520wwwꢀwhiteedcꢀcom

12 3 4 5 6

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