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EDI8L32128V

更新时间: 2022-04-23 23:00:11
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页数 文件大小 规格书
7页 190K
描述
128Kx32 CMOS High Speed Static RAM

EDI8L32128V 数据手册

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EDI8L32128V  
White Electronic Designs  
128Kx32 CMOS High Speed Static RAM  
FEATURES  
DESCRIPTION  
The EDI8L32128V is a high speed, 3.3V, four megabit  
density Static RAM. The device is available with access  
times of 12, 15 and 20ns, allowing the device to support  
60MHZ DSPs with no wait states. The high speed, 3.3V  
supply voltage and byte configurability make the device  
ideal for interfacing with Analog Devices ADSP-21062L or  
ADSP-21060L SHARC DSPs.  
128Kx32 bit CMOS Static  
Analog SHARCTM External Memory Solution  
ADSP-21060L  
ADSP-21062L  
Random Access Memory Array  
Fast Access Times: 12, 15 and 20ns  
User Configurable Organization  
with Minimal Additional Logic  
The device can be configured as a 128Kx32 and used to  
create a single chip external data memory solution for the  
SHARC (figure 1). Providing a 51ꢀ space savings when  
compared to four 128Kx8, 400mil wide plastic SOJs. The  
EDI8L32128V has a 10pf load on the data lines vs. 24pf for  
four plastic SOJs. Memory upgrades in the same footprint  
can be accomplished with the EDI8L32256V (256Kx32) or  
the EDI8L32512V (512KX32). This is covered in detail in  
the application report "The EDI's x32 MCM-L SRAM Family:  
Integrated Memory Solution for the Analog SHARC DSP"  
Master Output Enable and Write Control  
TTL Compatible Inputs and Outputs  
Fully Static, No Clocks  
Surface Mount Package  
68 Lead PLCC, No. 99 (JEDEC MO-47AE)  
Small Footprint, 0.990 Sq. In.  
Multiple Ground Pins for Maximum  
Noise Immunity  
Alternatively the device's chip enables can configure it as a  
256Kx16. A256Kx48 program memory array for the SHARC  
is created using three devices (figure 2). If this memory is  
too deep, two 128Kx24's (EDI8L24128V) can be used to  
create a 128Kx48 memory array.  
Single 3.3V ( 5ꢀ) Supply Operation  
Note: Solder Reflow temperature should not exceed 26ꢀ°C for 1ꢀ seconds  
PIN CONFIGURATIONS AND  
BLOCK DIAGRAM  
PIN NAMES  
AØ-A16  
EØ#-E3#  
W#  
Address Inputs  
Chip Enables (One per Byte)  
Master Write Enable  
Master Output Enable  
Common Data Input/Output  
Power (+3.3V 1ꢀ0)  
Ground  
G#  
60 DQ14  
DQØ-DQ31  
VCC  
VSS  
NC  
DQ17 10  
DQ18 11  
DQ19 12  
59 DQ13  
58 DQ12  
57  
V
SS  
V
SS 13  
56 DQ11  
55 DQ10  
54 DQ9  
53 DQ8  
DQ20 14  
DQ21 15  
DQ22 16  
DQ23 17  
No Connection  
52  
V
CC  
V
CC 18  
51 DQ7  
50 DQ6  
49 DQ5  
48 DQ4  
DQ24 19  
DQ25 20  
DQ26 21  
DQ27 22  
A0-A16  
17  
G#  
W#  
47  
V
SS  
V
SS 23  
46 DQ3  
45 DQ2  
44 DQ1  
DQ28 24  
DQ29 25  
DQ30 26  
E0#  
E1#  
E2#  
E3#  
DQ0-DQ7  
128Kx32  
Memory  
Array  
DQ8-DQ15  
DQ16-DQ23  
DQ24-DQ31  
Note: Pin 2 & 67 on the 64Kx32 (EDI8L3265C) and the 256Kx32 (EDI8L32256C) are  
word select pins.  
White Electronic Designs Corp. reserves the right to change products or specifications without notice.  
July 2004  
Rev. 6  
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  

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