Datasheet > EDI88512C

EDI88512C

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
WEDC		静态存储器
页数	文件大小	规格书
7页	320K
描述
512Kx8 Monolithic SRAM, CMOS

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EDI88512C 数据手册

EDI88512C

White Electronic Designs

512Kx8 Monolithic SRAM, CMOS

FEATURES

The EDI88512C is a 4 megabit Monolithic CMOS Static

RAM.

ꢀ

512Kx8 bit CMOS Static

ꢀ

Random Access Memory

The 32 pin DIP pinout adheres to the JEDEC evolutionary

standard for the four megabit device. Both the DIP and

CSOJ packages are pin for pin upgrades for the single chip

enable 128K x 8, the EDI88128C. Pins 1 and 30 become

the higher order addresses.

• Access Times of 70, 85, 100ns

• Data Retention Function (LP version)

• TTL Compatible Inputs and Outputs

• Fully Static, No Clocks

A Low Power version with Data Retention (EDI88512LP)

is also available for battery backed applications. Military

product is available compliant to Appendix A of MIL-PRF-

38535.

ꢀ

32 lead JEDEC Approved Evolutionary Pinout

• Ceramic Sidebrazed 600 mil DIP (Package 9)

• Ceramic SOJ (Package 140)

Single +5V ( 10ꢀ) Supply Operation

* This product is subject to change without notice.

FIGURE 1 – PIN CONFIGURATION

PIN DESCRIPTION

I/O0-7

A0-18

WE#

CS#

OE#

V_CC

Data Inputs/Outputs

Address Inputs

Write Enables

Chip Selects

Output Enable

Power (+5V 10ꢀ%

Ground

32 PIN

TOP VIEW

32 Vcc

31 A15

30 A17

29 WE#

28 A13

27 A8

A18

A16

A14

A12

V_SS

Not Connected

26 A9

32 pin

Evolutionary

25 A11

24 OE#

23 A10

22 CS#

21 I/O7

20 I/O6

19 I/O5

18 I/O4

17 I/O3

BLOCK DIAGRAM

Memory Array

I/O0

I/O1

I/O2 15

Vss

Address

Buffer

Address

Decoder

I/O

A0-18

I/O0-7

Circuits

WE#

CS#

OE#

White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice.

February 2001

Rev. 11

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6 7

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