Datasheet > EDI816256CA

EDI816256CA

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
WEDC		静态存储器
页数	文件大小	规格书
7页	270K
描述
256Kx16 MONOLITHIC SRAM, SMD 5962-96795

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EDI816256CA 数据手册

EDI816256CA

White Electronic Designs

256Kx16 MONOLITHIC SRAM, SMD 5962-96795

The EDI816256CAis a 4 megabit Monolithic CMOS Static

RAM.

FEATURES

ꢀ

256Kx16 bit CMOS Static

The EDI816256CA uses 16 common input and output

lines and has an output enable pin which operates faster

than address access time at read cycle. The device allows

upper and lower byte access by use of the data byte control

pins (LB#, UB#).

ꢀ

Random Access Memory

• Access Times of 17, 20, 25, 35ns

• Data Retention Function (LPA version)

• TTL Compatible Inputs and Outputs

• Fully Static, No Clocks

The devices are available in a fully hermetic 44 lead

ceramic SOJ and a 44 lead Ceramic Flatpack. The Ceramic

SOJ is pin for pin compatible with the commercially

available plastic SOJ. This allows the user the luxury of

designing a board that can be used for both the commercial

and military market.

ꢀ

44 lead JEDEC Approved Revolutionary Pinout

• Ceramic SOJ (Package 322)

• Ceramic Flatpack (Package 323)

Single +5V ( 10ꢀ) Supply Operation

ALow Power version with Data Retention (EDI816256LPA)

is also available for battery backed applications. Military

product is available compliant to Appendix A of MIL-PRF-

38535.

PIN CONFIGURATION

TOP VIEW

PIN DESCRIPTION

A0-17

LB# (I/O1-8)

UB# (I/O9-16)

I/O1-16

CS#

Address Inputs

Lower-Byte Control (I/O1-8)

Upper-Byte Control (I/O9-16)

Data Input/Output

Chip Select

A17

A16

A15

OE#

UB#

LB#

CS#

I/O1

I/O2

I/O3

I/O4

V_CC

V_SS

I/O5

I/O6

I/O7

I/O8

WE#

I/O16

I/O15

I/O14

I/O13

V_SS

OE#

Output Enable

WE#

Write Enable

V_CC

+5.0V Power

V_SS

Ground

V_CC

I/O12

I/O11

I/O10

I/O9

A14

A13

A12

A11

No Connection

A10

August 2004

Rev. 8

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6 7

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