Datasheet > EDI2CG472256V

EDI2CG472256V

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
WEDC		/
页数	文件大小	规格书
11页	203K
描述
8 Megabyte Sync/Sync Burst, Dual Key DIMM

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EDI2CG472256V 数据手册

EDI2CG472256V

White Electronic Designs

ADVANCED*

8 Megabyte Sync/Sync Burst, Dual Key DIMM

FEATURES

DESCRIPTION

The EDI2CG472256VxxD2 is a Synchronous/Synchronous

Burst SRAM, 84 position Dual Key; Double High DIMM (168

contacts) Module, organized as 4x256Kx72. The Module

contains sixteen (16) Synchronous Burst Ram Devices,

packaged in the industry standard JEDEC 14mmx20mm

TQFP placed on a Multilayer FR4 Substrate. The module

architecture is defined as a Sync/Sync Burst, Flow-

Through, with support for either linear or sequential burst.

This module provides High Performance, 2-1-1-1 accesses

when used in Burst Mode, and used as a Synchronous Only

Mode, provides a high performance cost advantage over

BiCMOS aysnchronous device architectures.

ꢀ

4x256Kx72 Synchronous, Synchronous Burst

Flow-Through Architecture

Linear and Sequential Burst Support via MODE pin

Clock Controlled Registered Module Enable (EM#)

Clock Controlled Registered Bank Enables (E1#, E2#,

E3#, E4#)

Clock Controlled Byte Write Mode Enable (BWE#)

Clock Controlled Byte Write Enables (BW1# - BW8#)

Clock Controlled Registered Address

Clock Controlled Registered Global Write (GW#)

Aysnchronous Output Enable (G#)

Internally Self-timed Write

Individual Bank Sleep Mode enables (ZZ₁, ZZ₂, ZZ₃, ZZ₄)

Gold Lead Finish

3.3V +10%, - 5% Operation

ꢀ

Synchronous Only operations are performed via strapping

ADSC# Low, and ADSP# / ADV# High, which provides for

Ultra Fast Accesses in Read Mode while providing for

internally self-timed Early Writes.

Synchronous/Synchronous Burst operations are in relation

to an externally supplied clock, Registered Address,

Registered Global Write, Registered Enables as well as

an Asynchronous Output enable. This Module has been

deﬁned with full ﬂexibility, which allows individual control

of each of the eight bytes, as well as Quad Words in both

Read and Write Operations.

Access Speed(s): TKHQV=9, 10, 12, 15ns

Common Data I/O

High Capacitance (30pf) drive, at rated Access Speed

Single Total Array Clock

Multiple Vcc and Gnd

*This product is under development, is not qualiﬁed or characterized and is subject to

change or cancellation without notice.

White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice.

July 1999

Rev 1

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6 7...11

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