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DM9000 PDF预览

DM9000

更新时间: 2024-02-09 09:41:24
品牌 Logo 应用领域
联杰 - DAVICOM 控制器以太网局域网(LAN)标准
页数 文件大小 规格书
53页 596K
描述
ISA to Ethernet MAC Controller with Integrated 10/100 PHY

DM9000 技术参数

是否Rohs认证: 符合生命周期:Contact Manufacturer
包装说明:LFQFP, QFP100,.63SQ,20Reach Compliance Code:unknown
HTS代码:8542.31.00.01风险等级:5.69
地址总线宽度:6边界扫描:NO
总线兼容性:ISA最大时钟频率:25 MHz
通信协议:BIT, BYTE, ETHERNET数据编码/解码方法:NRZ; NRZI; BIPH-LEVEL(MANCHESTER)
最大数据传输速率:12.5 MBps外部数据总线宽度:32
JESD-30 代码:S-PQFP-G100长度:14 mm
低功率模式:YES串行 I/O 数:4
端子数量:100最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP100,.63SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm子类别:Serial IO/Communication Controllers
最大压摆率:100 mA最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:14 mmuPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches:1

DM9000 数据手册

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DM9000  
ISA to Ethernet MAC Controller with Integrated 10/100 PHY  
1. General Description  
The DM9000 is a fully integrated and cost-effective  
single chip Fast Ethernet MAC controller with a  
general processor interface, a 10/100M PHY and 4K  
Dword SRAM. It is designed with low power and high  
performance process that support 3.3V with 5V  
tolerance.  
different processors. The PHY of the DM9000 can  
interface to the UTP3, 4, 5 in 10Base-T and UTP5 in  
100Base-TX. It is fully compliant with the IEEE 802.3u Spec.  
Its auto-negotiation function will automatically configure the  
DM9000 to take the maximum advantage of its abilities. The  
DM9000 also supports IEEE 802.3x full- duplex flow control.  
This programming of the DM9000 is very simple, so user  
can port the software drivers to any system easily.  
The DM9000 also provides a MII interface to connect  
HPNA device or other transceivers that support MII  
interface. The DM9000 supports 8-bit, 16-bit and  
32-bit uP interfaces to internal memory accesses for  
2. Block Diagram  
EEPROM  
Interface  
External MII  
Interface  
LED  
PHYceiver  
MAC  
TX Machine  
100 Base-TX  
transceiver  
100 Base-TX  
PCS  
Control &Status  
Registers  
Memory  
Management  
MII  
TX+/-  
RX+/-  
10 Base-T  
Tx/Rx  
RX Machine  
Internal  
SRAM  
MII Management  
Control  
Autonegotiation  
& MII Register  
Final  
1
Version: DM9000-DS-F03  
April 23, 2009  

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