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DDU8C-5150 PDF预览

DDU8C-5150

更新时间: 2024-01-10 08:13:59
品牌 Logo 应用领域
DATADELAY 延迟线逻辑集成电路
页数 文件大小 规格书
4页 51K
描述
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE

DDU8C-5150 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:DIP
包装说明:DIP,针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.71JESD-30 代码:R-XDIP-T8
JESD-609代码:e3逻辑集成电路类型:PASSIVE DELAY LINE
功能数量:1抽头/阶步数:5
端子数量:8最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:UNSPECIFIED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED可编程延迟线:NO
认证状态:Not Qualified座面最大高度:7.874 mm
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:NO
温度等级:MILITARY端子面层:Tin (Sn)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
总延迟标称(td):150 ns宽度:7.62 mm
Base Number Matches:1

DDU8C-5150 数据手册

 浏览型号DDU8C-5150的Datasheet PDF文件第2页浏览型号DDU8C-5150的Datasheet PDF文件第3页浏览型号DDU8C-5150的Datasheet PDF文件第4页 
DDU8C  
Ò
5-TAP, HCMOS-INTERFACED  
FIXED DELAY LINE  
(SERIES DDU8C)  
data  
delay  
3
devices, inc.  
FEATURES  
PACKAGES  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
VDD  
N/C  
T1  
N/C  
T3  
N/C  
T5  
IN  
N/C  
N/C  
T2  
N/C  
T4  
IN  
T2  
VDD  
·
·
·
·
·
·
Five equally spaced outputs  
Fits standard 8-pin DIP socket  
Low profile  
1
2
3
4
8
T1  
T3  
T5  
7
6
5
T4  
GND  
Auto-insertable  
8
GND  
Input & outputs fully CMOS interfaced & buffered  
DDU8C-xx  
DDU8C-xxA1 Gull-Wing  
DDU8C-xxB1 J-Lead  
DIP  
10 T2L fan-out capability  
Military SMD  
DDU8C-xxMD1  
DDU8C-xxMD4  
DDU8C-xxM Military DIP  
FUNCTIONAL DESCRIPTION  
PIN DESCRIPTIONS  
The DDU8C-series device is a 5-tap digitally buffered delay line. The  
signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an  
amount determined by the device dash number (See Table). The total  
delay of the line is measured from IN to T5. The nominal tap-to-tap delay  
increment is given by one-fifth of the total delay.  
IN  
Signal Input  
T1-T5 Tap Outputs  
VDD +5 Volts  
GND Ground  
DASH NUMBER SPECIFICATIONS  
SERIES SPECIFICATIONS  
Part  
Number  
Total  
Delay (ns)  
50 ± 2.5  
60 ± 3.0  
Delay Per  
Tap (ns)  
·
·
·
·
Minimum input pulse width: 40% of total delay  
Output rise time: 8ns typical  
Supply voltage: 5VDC ± 5%  
Supply current: ICCL = 40ma typical  
ICCH = 10ma typical  
Operating temperature: 0° to 70° C  
Temp. coefficient of total delay: 300 PPM/°C  
DDU8C-5050  
DDU8C-5060  
DDU8C-5075  
DDU8C-5100  
DDU8C-5125  
DDU8C-5150  
DDU8C-5175  
DDU8C-5200  
DDU8C-5250  
10.0 ± 3.0  
12.0 ± 3.0  
15.0 ± 3.0  
20.0 ± 3.0  
25.0 ± 3.0  
30.0 ± 3.0  
35.0 ± 4.0  
40.0 ± 4.0  
50.0 ± 5.0  
75 ± 4.0  
100 ± 5.0  
125 ± 6.5  
150 ± 7.5  
175 ± 8.0  
200 ± 10.0  
250 ± 12.5  
·
·
NOTE: Any dash number between 5004 and 5250  
not shown is also available.  
20%  
20%  
20%  
20%  
20%  
VDD IN  
T1  
T2  
T3  
T4  
T5 GND  
DDU8C Functional diagram  
Ó1997 Data Delay Devices  
Doc #97013  
1/28/97  
DATA DELAY DEVICES, INC.  
3 Mt. Prospect Ave. Clifton, NJ 07013  
1

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