BUS -6 1 5 5 9 S ERIES
MIL-S TD-1 5 5 3 B NOTICE 2
ADVANCED INTEGRATED MUX HYBRIDS
WITH ENHANCED RT FEATURES (AIM-HY’e r)
DESCRIPTION
FEATURES
DDC’s BUS-61559 series of Advanced buffers to provide a direct interface to
Integrated Mux Hybrids with enhanced a host processor bus. Alternatively,
RT Features (AIM-HY’er) comprise a the buffers may be operated in a fully
complete interface between a micro- transparent mode in order to interface
• Complete Integrated 1553B
Notice 2 Interface Terminal
processor and
a MIL-STD-1553B to up to 64K words of external shared
• Functlonal Superset of BUS-
61553 AlM-HYSeries
Notice bus, implementing Bus RAM and/or connect directly to a com-
2
Controller (BC), Remote Terminal (RX, ponent set supporting the 20 MHz
and Monitor Terminal (MT) modes. STANAG-3910 bus.
• Internal Address and Data
Buffers for Dlrect Interface to
Processor Bus
Packaged in a single 78-pin DIP or
The memory management scheme
82-pin flat package the BUS-61559
for RT mode prevails an option for
series contains dual low-power trans-
separation of broadcast data, in com-
ceivers and encoder/decoders, com-
pliance with 1553B Notice 2. A circu-
plete BC/RT/MT protocol logic, memory
lar buffer option for RT message data
management and interrupt logic, 8K x 16
blocks offloads the host processor for
of shared static RAM, and a direct,
bulk data transfer applications.
• RT Subaddress Circular Buffers
to Support Bulk Data Transfers
buffered interface to a host processor bus.
• Optlonal Separatlon of
RT Broadcast Data
Another feature besides those listed
to the right, is a transmitter inhibit con-
trol for the individual bus channels.
The BUS-61559 includes a number of
advanced features in support of
MIL-STD-1553B Notice 2 and STANAG
• Internal Interrupt Status and
Time Tag Registers
3838. Other salient features of the
BUS-61559 serve to provide the bene-
fits of reduced board space require-
ments enhanced software flexibility,
and reduced host processor overhead
The BUS-61559 series hybrids oper-
ate over the full military temperature
range of -55 to +125”C and MIL-PRF-
38534 processing is available. The
hybrids are ideal for demanding mili-
tary and industrial microprocessor-to-
1553 applications
• Internal ST Command
Illegalization
The BUS-61559 contains internal
address latches and bidirectional data
• MIL-PRF-38534 Processing
Available
(ILLEGALIZATION
ILLENA
ILLEGALLIZATION
LOGIC
ENABLE)
8K x 16
DUAL
PORT
RAM
CLK IN (16MHz)
BUS-25679
8
7
5
4
1
LOW-POWER
TRANSCEIVER
A
2
3
DUAL
TX_INH_A
ENCODER/
DECODER
BC/RT/MT
PROTOCOL
DATA
BUFFERS*
(PROCESSOR
DATA)
MEMORY DATA
D15-D
BUS-25679
8
7
5
4
1
(PROCESSOR
ADDRESS)
LOW-POWER
TRANSCEIVER
A
A15-A
2
ADDRESS
LATCHES/
BUFFERS*
MEMORY ADDRESS
3
(ADDRESS
LATCH
CONTROL)
ADDR_LAT
TX_INH_A
TRANSPARENT/BUFFERED, MSTCLR,
STRBD, SELECT, MEM/REG, RD/WR
RTAD 4- , RTADP
BRO_ENA
RTFAIL
(RT ADDRESS)
(PROCESSOR
CONTROL)
MEMORY
MANAGEMENT,
SHARED
IOEN, READYD
INT
(BROADCAST
ENABLE)
(INTERRUPT
REQUEST)
RAM/
MEMEN-OUT,MEMWR, MEMOE
MEMENA-IN
(MEMORY
CONTROL)
PROCESSOR
INTERFACE,
INTERRUPT
LOGIC
(RTFAIL,
RTFLAG)
RTFLAG
(SUBSYSTEM
FLAG)
SSFLAG
(BROADCAST,
MESSAGE
TIMING, DATA
(TIME TAG
CLOCK)
TAGCLK
BCSTRCV, CMD_STR, TXDTA_STR
RXDTA_STR, MSG_ERR, INCMD
STROBE AND ERROR
INDICATORS)
BU-61559 BLOCK DIAGRAM
© 1990, 1999 Data Device Corporation
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