Ultra Low Power/Voltage CMOS SRAM
128K X 8 bit
BSI
BS62UV1027
• Data retention supply voltage as low as 1.2V
FEATURES
• Wide Vcc operation voltage :
C-grade : 1.8V ~ 3.6V
I-grade : 1.9V ~ 3.6V
(Vcc_min.=1.65V at 25oC)
• Ultra low power consumption :
• Easy expansion with CE2, CE1 and OE options
DESCRIPTION
The BS62UV1027 is a high performance, ultra low power CMOS
Static Random Access Memory organized as 131,072 words by 8 bits
and operates from a wide range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.05uA at 2.0V/25oC and maximum access time of 85ns at 85oC.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
Vcc = 2.0V C-grade : 7mA (Max.) operating current
I -grade : 8mA (Max.) operating current
0.05uA (Typ.) CMOS standby current
Vcc = 3.0V C-grade : 13mA (Max.) operating current
I- grade : 15mA (Max.) operating current
0.10uA (Typ.) CMOS standby current
• High speed access time :
The BS62UV1027 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
-85
-10
85ns (Max.)
100ns (Max.)
The BS62UV1027 is available in DICE form, JEDEC standard 32 pin
450mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP, 8mmx13.4
mm STSOP and 8mmx20mm TSOP.
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
PRODUCT FAMILY
POWER DISSIPATION
SPEED
(ns)
STANDBY
Operating
(ICC, Max)
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
PKG TYPE
(ICCSB1, Max)
C-grade:1.8~3.6V
I-grade:1.9~3.6V
Vcc=
3.0V
Vcc=
2.0V
Vcc=
3.0V
Vcc=
2.0V
-32
SOP
TSOP
BS62UV1027SC
BS62UV1027TC
BS62UV1027JC
BS62UV1027STC
BS62UV1027PC
BS62UV1027DC
BS62UV1027SI
BS62UV1027TI
BS62UV1027JI
BS62UV1027STI
BS62UV1027PI
BS62UV1027DI
-32
-32
STSOP 32
+0 O C to +70 O
C
C
1.8V ~ 3.6V
1.9V ~ 3.6V
1.3uA
0.5uA
1.0uA
13mA
7mA
8mA
SOJ
85/100
85/100
-
-32
PDIP
DICE
SOP
-32
-32
TSOP
-
SOJ 32
STSOP
-40 O C to +85 O
2.5uA
15mA
-32
32
PDIP-
DICE
BLOCK DIAGRAM
PIN CONFIGURATIONS
NC
A16
A14
A12
A7
1
VCC
A15
CE2
WE
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
A6
A7
A12
A14
A16
A15
A13
A8
3
4
5
A13
A8
Address
Memory Array
1027 x 1027
20
1027
A6
6
BS62UV1027SC
BS62UV1027SI
BS62UV1027PC
BS62UV1027PI
BS62UV1027JC
BS62UV1027JI
Row
Decoder
Input
A5
7
A9
A4
8
A11
OE
Buffer
A3
9
A2
10
11
12
13
14
15
16
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
A9
A11
A1
A0
DQ0
DQ1
DQ2
GND
1027
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
8
Column I/O
Write Driver
Sense Amp
8
8
Data
Output
Buffer
128
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
Column Decoder
14
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
CE2
CE1
WE
BS62UV1027TC
Control
BS62UV1027STC
BS62UV1027TI
BS62UV1027STI
Address Input Buffer
9
OE
Vdd
Gnd
10
11
12
13
14
15
16
A5 A4 A3 A2 A1 A0 A10
A6
A5
A4
A1
A2
A3
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Revision 2.1
Jan. 2004
R0201-BS62UV1027
1
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