Very Low Power/Voltage CMOS SRAM
1M X 8 bit
BSI
BS62LV8005
GENERAL DESCRIPTION
FEATURES
• Wide Vcc operation voltage : 4.5V ~ 5.5V
• Very low power consumption :
The BS62LV8005 is a high performance, very low power CMOS
Static Random Access Memory organized as 1,048,576 words by 8 bits
and operates from a wide range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
3uA and maximum access time of 55ns in 5V operation.
Vcc = 5V C-grade: 45mA (Max.) operation current
I -grade: 50mA (Max.) operating current
3uA (Typ.) CMOS standby current
• High speed access time :
-55
-70
55ns (Max) at Vcc = 5V
70ns (Max) at Vcc = 5V
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable(CE2) and active LOW output
enable (OE) and three-state output drivers.
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
The BS62LV8005 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
The BS62LV8005 is available in 44 pin TSOP2 and 48-pin BGA type.
PRODUCT FAMILY
POWER DISSIPATION
SPEED
( ns )
(SI TAN,DMBaYx )
Operating
PRODUCT
FAMILY
OPERATING
Vcc
( I , Max )
CC
CCSB1
PKG TYPE
TEMPERATURE
RANGE
Vcc=5V
55 / 70
55 / 70
Vcc=5V
30uA
Vcc=5V
45mA
50mA
BS62LV8005EC
BS62LV8005BC
BS62LV8005EI
BS62LV8005BI
TSOP2-44
+0OC to +70OC 4.5V ~ 5.5V
-40OC to +85OC 4.5V ~ 5.5V
BGA-48-0810
TSOP2-44
50uA
BGA-48-0810
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A5
2
A3
A6
3
A2
A7
4
A1
OE
5
A0
CE2
A8
A13
A17
A15
6
CE1
7
NC
NC
8
NC
NC
Address
A18
9
DQ0
DQ7
DQ6
GND
VCC
DQ5
DQ4
NC
Memory Array
2048 X 4096
22
10
2048
BS62LV8005EC
DQ1
A16
A14
A12
A7
Row
11
VCC
Input
BS62LV8005EI
12
GND
13
DQ2
Decoder
Buffer
14
DQ3
15
A6
NC
16
NC
NC
A9
A5
17
WE
A4
18
A19
A10
A11
A12
A13
A14
19
A18
4096
20
A17
21
A16
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
22
8
Column I/O
A15
Input
Buffer
Write Driver
Sense Amp
1
2
3
4
5
6
8
8
Data
A
B
C
D
E
F
OE
A0
A3
A1
A4
A2
CE2
NC
NC
512
Output
Buffer
Column Decoder
18
NC
NC
NC
D1
CE1
NC
CE1
CE2
WE
OE
A5
A6
D0
VSS
VCC
D4
Control
Address Input Buffer
A17
VCC
A14
A12
A9
A7
D5
D6
VCC
VSS
Vdd
Gnd
A11A9 A8 A3 A2 A1 A0A10 A19
D2
NC
NC
A16
A15
A13
A10
D7
NC
A19
D3
NC
NC
G
H
WE
A11
A18
A8
48-Ball CSP top View
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
Revision 2.4
April 2002
R0201-BS62LV8005
1
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