Very Low Power/Voltage CMOS SRAM
512K X 8 bit
BSI
BS62LV4006
FEATURES
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• Three state outputs and TTL compatible
• Wide Vcc operation voltage : 2.4V ~ 5.5V
• Very low power consumption :
Vcc = 3.0V C-grade: 29mA (@55ns) operating current
I -grade: 30mA (@55ns) operating current
C-grade: 24mA (@70ns) operating current
I -grade: 25mA (@70ns) operating current
0.45uA (Typ.) CMOS standby current
DESCRIPTION
The BS62LV4006 is a high performance, very low power CMOS
Static Random Access Memory organized as 524,288 words by 8 bits
and operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.45uA at 3.0V/25oC and maximum access time of 55ns at 3.0V/85oC.
Easy memory expansion is provided by an active LOW chip enable
(CE) , and active LOW output enable (OE) and three-state output
drivers.
Vcc = 5.0V C-grade: 68mA (@55ns) operating current
I -grade: 70mA (@55ns) operating current
C-grade: 58mA (@70ns) operating current
I -grade: 60mA (@70ns) operating current
2.0uA (Typ.) CMOS standby current
• High speed access time :
-55
-70
55ns
70ns
The BS62LV4006 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV4006 is available in the JEDEC standard 32L SOP, TSOP
, PDIP, TSOP II and STSOP package.
• Automatic power down when chip is deselected
• Fully static operation
PRODUCT FAMILY
POWER DISSIPATION
SPEED
( ns )
STANDBY
Operating
PKG
TYPE
PRODUCT
FAMILY
OPERATING
Vcc
( I CCSB1 , Max )
( I CC , Max )
TEMPERATURE RANGE
55ns:3.0~5.5V
70ns:2.7~5.5V
Vcc =5.0V
Vcc = 3.0V
70ns
Vcc =5.0V
Vcc = 3.0V
70ns
-
BS62LV4006TC
BS62LV4006STC
BS62LV4006SC
BS62LV4006EC
BS62LV4006PC
BS62LV4006TI
BS62LV4006STI
BS62LV4006SI
BS62LV4006EI
BS62LV4006PI
TSOP 32
-
STSOP 32
SOP 32
+0 O C to +70O
C
C
2.4V ~ 5.5V
2.4V ~ 5.5V
55 / 70
55 / 70
5uA
30uA
60uA
24mA
25mA
58mA
-
-
TSOP2 32
-
32
PDIP
-
TSOP 32
-
STSOP 32
SOP 32
TSOP2 32
PDIP 32
O
40 C to +85O
10uA
60mA
-
-
-
-
BLOCK DIAGRAM
PIN CONFIGURATIONS
A18
A16
A14
A12
A7
1
VCC
A15
A17
WE
A13
A8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
A13
A17
A15
A18
A16
A14
A12
A7
3
4
Address
Input
Memory Array
5
22
2048
Row
Decoder
A6
6
A5
7
A9
2048 X 2048
A4
BS62LV4006SC
BS62LV4006SI
BS62LV4006EC
BS62LV4006EI
BS62LV4006PC
BS62LV4006PI
8
A11
OE
Buffer
A3
9
A6
A5
A4
A2
10
11
12
13
14
15
16
A10
CE
A1
A0
DQ7
DQ6
DQ5
DQ4
DQ3
2048
DQ0
DQ1
DQ2
GND
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
8
Column I/O
Write Driver
Sense Amp
8
8
Data
Output
Buffer
256
1
2
3
4
5
6
7
8
32
A11
A9
A8
OE
A10
CE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Column Decoder
16
A13
WE
A17
A15
VCC
A18
A16
A14
A12
A7
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
CE
WE
OE
Control
BS62LV4006TC
BS62LV4006STC
BS62LV4006TI
BS62LV4006STI
Address Input Buffer
9
10
11
12
13
14
15
16
Vdd
GND
A11 A9 A8 A3 A2 A1 A0 A10
A6
A5
A4
A1
A2
A3
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Revision 1.1
Jan. 2004
R0201-BS62LV4006
1
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