Very Low Power/Voltage CMOS SRAM
256K X 8 bit
BSI
BS62LV2006
FEATURES
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2, CE1, and OE options
• Wide Vcc operation voltage : 2.4V~5.5V
• Very low power consumption :
Vcc = 3.0V C-grade : 22mA (@55ns) operating current
I- grade : 23mA (@55ns) operating current
C-grade : 17mA (@70ns) operating current
I- grade : 18mA (@70ns) operating current
0.3uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade : 53mA (@55ns) operating current
I- grade : 55mA (@55ns) operating current
C-grade : 43mA (@70ns) operating current
I- grade : 45mA (@70ns) operating current
1.0uA (Typ.) CMOS standby current
DESCRIPTION
The BS62LV2006 is a high performance, very low power CMOS
Static Random Access Memory organized as 262,144 words by 8 bits
and operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.3uA at 3.0V/25oC and maximum access time of 55ns at 3.0V/85oC.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
• High speed access time :
-55
-70
55ns
70ns
The BS62LV2006 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV2006 is available in DICE form, JEDEC standard 32 pin
450mil Plastic SOP, 8mmx13.4mm STSOP and 8mmx20mm TSOP.
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
PRODUCT FAMILY
POWER DISSIPATION
SPEED
( ns )
STANDBY
Operating
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
( ICCSB1, Max )
( ICC, Max )
PKG TYPE
55ns :3.0~5.5V
70ns :2.7~5.5V
Vcc=3.0V
70ns
Vcc=5.0V
70ns
Vcc=3.0V
Vcc=5.0V
BS62LV2006DC
BS62LV2006TC
BS62LV2006STC
BS62LV2006SC
BS62LV2006DI
BS62LV2006TI
BS62LV2006STI
BS62LV2006SI
DICE
TSOP-32
STSOP-32
SOP-32
DICE
TSOP-32
STSOP-32
SOP-32
+0 O C to +70O
-40 O C to +85O
C
C
2.4V ~5.5V
2.4V ~ 5.5V
55/70
55/70
3.0uA
5.0uA
10uA
17mA
43mA
45mA
30uA
18mA
BLOCK DIAGRAM
PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A13
A17
A13
WE
CE2
A15
VCC
A17
A16
A14
A12
A7
A15
A16
A14
Address
Memory Array
20
1024
BS62LV2006TC
BS62LV2006STC
BS62LV2006TI
BS62LV2006STI
Row
Decoder
Input
A12
A7
A6
A5
A4
9
1024 x 2048
Buffer
10
11
12
13
14
15
16
A6
A5
A4
A1
A2
A3
2048
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
8
Column I/O
Write Driver
Sense Amp
A17
A16
A14
A12
A7
1
VCC
A15
CE2
WE
32
8
2
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
8
Data
Output
Buffer
3
256
4
5
A13
A8
Column Decoder
16
A6
6
A5
7
A9
BS62LV2006SC
BS62LV2006SI
A4
8
A11
OE
CE1
CE2
A3
9
Control
Address Input Buffer
A2
10
11
12
13
14
15
16
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
WE
OE
Vdd
Gnd
A1
A0
DQ0
DQ1
DQ2
GND
A9 A8 A3 A2 A1 A0 A10
A11
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Revision 1.1
Jan. 2004
R0201-BS62LV2006
1
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