Very Low Power/Voltage CMOS SRAM
2M X 8 bit
BSI
BS62LV1605
FEATURES
GENERAL DESCRIPTION
• Vcc operation voltage : 4.5V ~ 5.5V
• Very low power consumption :
The BS62LV1605 is a high performance , very low power CMOS Static
Random Access Memory organized as 2048K words by 8 bits and
operates from a range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
15uA at 5.0V/25oC and maximum access time of 55ns at 5.0V/85oC.
Easy memory expansion is provided by an active LOW chip enable(CE1)
, an active HIGH chip enable (CE2) and active LOW output enable (OE)
and three-state output drivers.
Vcc = 5.0V C-grade: 113mA (@55ns) operating current
I -grade: 115mA (@55ns) operating current
C-grade: 90mA (@70ns) operating current
I -grade: 92mA (@70ns) operating current
15uA (Typ.) CMOS standby current
• High speed access time :
-55
-70
55ns
70ns
The BS62LV1605 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV1605 is available in 48B BGA and 44L TSOP2 packages.
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
PRODUCT FAMILY
POWER DISSIPATION
SPEED
( ns )
STANDBY
Operating
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
( ICCSB1, Max )
( ICC, Max )
PKG TYPE
Vcc=5V
70ns
Vcc=5V
55ns
55ns : 4.5~5.5V
70ns : 4.5~5.5V
Vcc=5V
110uA
220uA
BS62LV1605EC
BS62LV1605FC
BS62LV1605EI
BS62LV1605FI
TSOP2-44
BGA-48-0912
TSOP2-44
+0O C to +70OC 4.5V ~ 5.5V
-40OC to +85OC 4.5V ~ 5.5V
55 / 70
55 / 70
113mA
115mA
90mA
92mA
BGA-48-0912
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A2
A1
A0
CE1
NC
NC
DQ0
DQ1
VCC
GND
DQ2
DQ3
NC
A20
A5
A6
A7
OE
CE2
A8
NC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
A20
A13
A17
NC
DQ7
DQ6
GND
VCC
DQ5
DQ4
NC
BS62LV1605EC
BS62LV1605EI
A15
Address
Memory Array
A18
A16
A14
A12
A7
24
4096
Row
Input
4096 X 4096
Decoder
NC
A9
Buffer
WE
A19
A18
A17
A16
A15
18
19
20
21
A6
A5
A4
A10
A11
A12
A13
A14
22
4096
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
1
2
3
4
5
6
8
Column I/O
Write Driver
Sense Amp
A
B
C
D
E
F
OE
A0
A1
A2
CE2
NC
NC
NC
8
8
Data
Output
Buffer
NC
NC
A3
A5
A4
CE1
NC
512
A6
D0
D4
Column Decoder
18
VSS
A17
VCC
A7
VCC
VSS
D1
D2
D5
D6
CE1
CE2
WE
OE
Control
A16
A15
A13
A10
VCC
D3
Address Input Buffer
D7
NC
NC
NC
WE
A11
A14
A12
A9
Vdd
Gnd
A11A9 A8 A3 A2 A1 A0A10 A19
A20
G
H
NC
A18
A8
A19
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Revision 2.1
Jan. 2004
R0201-BS62LV1605
1
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