Ultra Low Power/Voltage CMOS SRAM
128K X 16 bit
BSI
BS616UV2019
FEATURES
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
• Data retention supply voltage as low as 1.0V
• Wide Vcc operation voltage :
C-grade: 1.8V~3.6V
I-grade: 1.9V~3.6V
(Vcc_min.=1.65V at 25oC)
DESCRIPTION
• Ultra low power consumption :
The BS616UV2019 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a wide range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.2uA at 2.0V/25oC and maximum access time of 85ns at 85oC.
Easy memory expansion is provided by active LOW chip enable (CE),
active LOW output enable(OE) and three-state output drivers.
The BS616UV2019 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
Vcc = 2.0V
C-grade: 8mA (Max.) operating current
I -grade: 10mA (Max.) operating current
0.20uA (Typ.) CMOS standby current
C-grade: 11mA (Max.) operating current
I -grade: 13mA (Max.) operating current
0.30uA (Typ.) CMOS standby current
Vcc = 3.0V
• High speed access time :
-85
-10
85ns (Max.)
100ns (Max.)
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
The BS616UV2019 is available in DICE form, JEDEC standard 48-pin
TSOP Type I package and 48-ball BGA package.
PRODUCT FAMILY
POWER DISSIPATION
SPEED
( ns )
STANDBY
Operating
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
( ICCSB1, Max )
( ICC, Max )
PKG TYPE
C-grade:1.8~3.6V
I-grade:1.9~3.6V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
BS616UV2019DC
BS616UV2019TC
BS616UV2019AC
BS616UV2019DI
BS616UV2019TI
BS616UV2019AI
DICE
+0 O C to +70O
-40 O C to +85O
C
C
11mA
13mA
8mA
2.0uA
3.0uA
3.0uA
85/100
85/100
1.8V ~3.6V
1.9V ~ 3.6V
TSOP1-48
BGA-48-0608
DICE
TSOP1-48
BGA-48-0608
10mA
5.0uA
PIN CONFIGURATIONS
BLOCK DIAGRAM
A15
1
48
47
46
A16
NC
A14
A13
A12
A11
A10
A9
VSS
IO15
IO7
A8
A13
IO14
IO6
A15
Address
A8
IO13
IO5
20
A16
A14
1024
NC
NC
/WE
CE2
NC
/UB
/LB
NC
NC
A7
9
Input
10
IO12
IO4
Row
Memory Array
1024 x 2048
A12
A7
37
VCC
IO11
IO3
BS616UV2019TC
BS616UV2019TI
Buffer
13
Decoder
IO10
IO2
A6
A5
A4
16
17
IO9
IO1
A6
IO8
2048
A5
IO0
A4
/OE
VSS
Data
Input
Buffer
A3
27
25
16
16
16
Column I/O
A2
/CE
A0
DQ0
A1
24
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
1
2
3
4
5
6
128
Data
Output
16
A
B
C
D
E
F
LB
D8
OE
UB
A0
A3
A1
A4
A2
N.C.
D0
Buffer
Column Decoder
DQ15
CE
D1
D3
D9
D10
D11
D12
D13
A5
A6
D2
14
CE2,CE
WE
N.C.
VSS
VCC
A7
VCC
VSS
Control
Address Input Buffer
OE
UB
N.C.
A14
A12
A9
A16
A15
A13
A10
D4
D5
LB
A11 A9 A3 A2 A1
A0 A10
D14
D15
N.C.
D6
D7
Vcc
Gnd
WE
G
H
N.C.
A8
N.C.
A11
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Revision 1.1
R0201-BS616UV2019
1
Jan.
2004
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