Very Low Power/Voltage CMOS SRAM
512K X 16 bit
(Single CE Pin)
BSI
BS616LV8010
FEATURES
DESCRIPTION
• Vcc operation voltage : 2.7~3.6V
The BS616LV8010 is a high performance, very low power CMOS Static
Random Access Memory organized as 524,288 words by 16 bits and
operates from a range of 2.7V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 1.5uA at 3V/25oC and maximum access time of 55ns at 3V/85oC.
Easy memory expansion is provided by an active LOW chip enable (CE)
,active LOW output enable(OE) and three-state output drivers.
The BS616LV8010 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
• Very low power consumption :
Vcc = 3.0V C-grade: 30mA (@55ns) operating current
I -grade: 31mA (@55ns) operating current
C-grade: 24mA (@70ns) operating current
I -grade: 25mA (@70ns) operating current
1.5uA (Typ.) CMOS standby current
• High speed access time :
-55
-70
55ns
70ns
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
The BS616LV8010 is available in 48B BGA and 44L TSOP2 packages.
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
PRODUCT FAMILY
POWER DISSIPATION
SPEED
( ns )
STANDBY
Operating
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
( ICCSB1, Max )
( ICC, Max )
PKG TYPE
Vcc=3V
70ns
Vcc=3V
55ns
55ns : 3.0~3.6V
70ns : 2.7~3.6V
Vcc=3V
5uA
BS616LV8010EC
BS616LV8010FC
BS616LV8010EI
BS616LV8010FI
TSOP2-44
BGA-48-0912
TSOP2-44
+0O C to +70OC 2.7V ~ 3.6V
-40OC to +85OC 2.7V ~ 3.6V
55 / 70
55 / 70
30mA
31mA
24mA
25mA
10uA
BGA-48-0912
PIN CONFIGURATIONS
BLOCK DIAGRAM
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A2
A1
A0
CE
DQ0
DQ1
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
Vss
A4
A3
A2
A1
A0
Address
Input
22
2048
9
DQ2
DQ3
Vcc
A17
A16
Row
Memory Array
2048 x 4096
10
11
12
13
14
15
16
17
18
19
20
21
22
BS616LV8010EC
BS616LV8010EI
Buffer
Vss
Vcc
A15
A14
A13
A12
Decoder
DQ4
DQ5
DQ6
DQ7
WE
A18
A17
A16
A15
A14
DQ11
DQ10
DQ9
DQ8
A8
4096
A9
A10
A11
A12
A13
Data
Input
16
16
Column I/O
D0
Buffer
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
1
2
3
4
6
16
5
A2
256
Data
Output
16
LB
OE
A0
A1
NC
A
B
C
D
E
F
Buffer
Column Decoder
D15
D8
D9
UB
A3
A5
A4
A6
A7
CE
D1
D3
D0
D2
D10
D11
16
CE
V
A17
V
CC
SS
SS
CC
WE
OE
UB
Control
Address Input Buffer
A16
A 15
A13
A10
D4
D5
VSS
A14
A12
A9
V
V
D12
D13
D6
D14
D15
A18
LB
A11 A10 A9 A8 A7
A6 A5 A18
WE
A11
D7
N.C
A8
Vcc
Vss
G
H
NC
48-Ball CSP top View
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Revision 1.1
R0201-BS616LV8010
1
Jan.
2004
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