Very Low Power/Voltage CMOS SRAM
128K X 16 bit
BSI
BS616LV2017
FEATURES
• I/O Configuration x8/x16 selectable by LB and UB pin
• Vcc operation voltage : 4.5V ~ 5.5V
• Very low power consumption :
DESCRIPTION
Vcc = 5.0V C-grade: 60mA (@55ns) operating current
I -grade: 62mA (@55ns) operating current
C-grade: 53mA (@70ns) operating current
I -grade: 55mA (@70ns) operating current
1.0uA(Typ.) CMOS standbycurrent
The BS616LV2017 is a high performance , very low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
1.0uA at 5.0V/25oC and maximum access time of 55ns at 5.0V/85oC.
Easy memory expansion is provided by active LOW chip enable (CE),
active LOW output enable(OE) and three-state output drivers.
The BS616LV2017 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
• High speed access time :
-55
-70
55ns
70ns
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
The BS616LV2017 is available in DICE form , JEDEC standard 44-pin
TSOP Type II package and 48-ball BGA package.
PRODUCT FAMILY
POWER DISSIPATION
SPEED
( ns )
STANDBY
Operating
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
( ICCSB1, Max )
( ICC, Max )
PKG TYPE
55ns: 4.5~5.5V
70ns: 4.5~5.5V
Vcc=5.0V
Vcc=5.0V
70ns
55ns
BS616LV2017DC
BS616LV2017EC
BS616LV2017AC
BS616LV2017DI
BS616LV2017EI
BS616LV2017AI
DICE
+0 O C to +70O
-40 O C to +85O
C
C
4.5V ~5.5V
4.5V ~ 5.5V
55/70
55/70
53mA
55mA
10uA
60mA
TSOP2-44
BGA-48-0608
DICE
TSOP2-44
BGA-48-0608
62mA
30uA
PIN CONFIGURATIONS
BLOCK DIAGRAM
1
44
43
A4
A5
2
A3
A6
3
42
A2
A1
A7
4
41
A8
A13
OE
5
40
A0
UB
6
39
CE
LB
A15
7
Address
38
37
DQ0
DQ15
DQ14
20
8
9
A16
A14
1024
DQ1
36
Input
DQ2
DQ13
Row
Memory Array
1024 x 2048
10
35
DQ3
DQ12
A12
A7
BS616LV2017EC
BS616LV2017EI
11
12
13
14
15
16
17
18
19
20
21
22
34
33
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
GND
Buffer
Decoder
VCC
32
31
A6
A5
A4
DQ11
DQ10
DQ9
30
29
DQ8
2048
28
NC
Data
Input
Buffer
27
A16
A15
A14
A13
A12
A8
16
16
16
Column I/O
26
25
A9
DQ0
A10
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
24
A11
23
NC
128
Data
Output
1
2
3
4
5
6
16
Buffer
Column Decoder
DQ15
A
B
C
D
E
F
LB
D8
D9
OE
UB
A0
A3
A1
A4
A2
N.C.
D0
14
CE
D1
D3
CE
WE
OE
UB
Control
Address Input Buffer
D10
D11
D12
D13
A5
A6
D2
N.C.
VSS
A7
VCC
VSS
LB
A11 A9 A3 A2 A1
A0 A10
VCC
N.C.
A14
A12
A9
A16
A15
A13
A10
D4
D5
Vcc
Gnd
D14
D15
N.C.
D6
D7
WE
G
H
N.C.
A8
N.C.
A11
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Revision 1.1
R0201-BS616LV2017
1
Jan.
2004
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