Datasheet > AZ10ELT22

AZ10ELT22

更新时间： 2024-01-04 12:06:35

品牌	Logo	应用领域
AZM		转换器
页数	文件大小	规格书
6页	74K
描述
CMOS/TTL to Differential PECL Translator

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技术参数
数据手册

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AZ10ELT22 技术参数

是否Rohs认证：	符合	生命周期：	Contact Manufacturer
包装说明：	,	Reach Compliance Code：	compliant
风险等级：	5.68	Base Number Matches：	1

AZ10ELT22 数据手册

ARIZONA MICROTEK, INC.

AZ10ELT22

AZ100ELT22

CMOS/TTL to Differential PECL Translator

PACKAGE AVAILABILITY

FEATURES

PACKAGE

PART NUMBER

MARKING NOTES

•

Green / RoHS Compliant /

AZM10

ELT22

SOIC 8

AZ10ELT22D

1,2,4

Lead (Pb) Free package available

0.5ns Typical Propagation Delay

<100ps Typical Output to Output

•

SOIC 8 RoHS

Compliant / Lead

(Pb) Free

AZM10+

1,2,4

AZ10ELT22D+

AZ100ELT22D

AZ100ELT22D+

AZ10ELT22T

ELT22

Skew

AZM100

1,2,4

•

Differential PECL Outputs

Flow Through Pinouts

Operating Range of 3.0V to 5.5V

Direct Replacement for

ON Semiconductor MC10ELT22 &

MC100ELT22

SOIC 8

ELT22

SOIC 8 RoHS

Compliant / Lead

(Pb) Free

AZM100+

1,2,4

ELT22

AZT

1,2,4

LT22

TSSOP 8

TSSOP 8 RoHS

Compliant / Lead

(Pb) Free

•

IBIS Model Files Available on

Arizona Microtek Website

AZT+

1,2,4

AZ10ELT22T+

AZ100ELT22T

AZ100ELT22T+

LT22

AZH

1,2,4

LT22

TSSOP 8

TSSOP 8 RoHS

Compliant / Lead

(Pb) Free

AZH+

1,2,4

LT22

DESCRIPTION

Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)

Tape & Reel.

Date code format: “Y” or “YY” for year followed by “WW” for week.

Parts marked JNB for date codes prior to 4WW (prior to 2004).

Date code “YWW” or “YYWW” on underside of part.

The AZ10/100ELT22 is a dual

CMOS/TTL to differential PECL

translator. Because PECL (Positive ECL)

levels are used, only V_CCand ground are

required. The small outline packaging and the low skew, dual gate design of the ELT22 makes it ideal for

applications that require the translation of a clock and a data signal.

The ELT22 is available in both PECL standards: the 10ELT is compatible with PECL 10K logic levels while

the 100ELT is compatible with PECL 100K logic levels.

NOTE: Specifications in PECL tables are valid when thermal equilibrium is established.

LOGIC DIAGRAM AND

PINOUT

PIN DESCRIPTION

Q0, Q¯¯0, Q1, Q¯¯1

D0, D1

FUNCTION

Differential PECL Outputs

CMOS/TTL Input

Positive Supply

V_CC

GND

Ground

1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541

www.azmicrotek.com

12 3 4 5 6

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