Datasheet > AT940

AT940

更新时间： 2022-02-26 12:47:29

品牌	Logo	应用领域
POSEICO		/
页数	文件大小	规格书
6页	618K
描述
PHASE CONTROL THYRISTOR

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数据手册

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AT940 数据手册

POSEICO SPA

Via Pillea 42-44, 16153 Genova - ITALY

Tel. + 39 010 8599400 - Fax + 39 010 8682006

Sales Office:

Tel. + 39 010 8599400 - sales@poseico.com

PHASE CONTROL THYRISTOR

AT940

Repetitive voltage up to

Mean on-state current

Surge current

2900 V

4687 A

75 kA

FINAL SPECIFICATION

Feb. 17 - Issue: 6

[°C]

Symbol

Characteristic

Conditions

Value

Unit

BLOCKING

V RRM

V RSM

V DRM

I RRM

I DRM

Repetitive peak reverse voltage

Non-repetitive peak reverse voltage

Repetitive peak off-state voltage

Repetitive peak reverse current

Repetitive peak off-state current

125

2900

3000

2900

300

V=VRRM

V=VDRM

300

CONDUCTING

I T (AV)

I TSM

I² t

Mean on-state current

Surge on-state current

I² t

180° sin, 50 Hz, Th=55°C, double side cooled

180° sin, 50 Hz, Tc=85°C, double side cooled

sine wave, 10 ms

4687

3638

125

75,0

without reverse voltage

28125 x1E3

1,55

A²s

V T

On-state voltage

On-state current =

7500 A

V T(TO)

r T

Threshold voltage

On-state slope resistance

125

1,00

0,070

mohm

SWITCHING

di/dt

dv/dt

Critical rate of rise of on-state current, min.

Critical rate of rise of off-state voltage, min.

Gate controlled delay time, typical

Circuit commutated turn-off time, typical

Reverse recovery charge

From 75% VDRM, gate 10V 5ohm

Linear ramp up to 70% of VDRM

VD=100V, gate source 10V, 10 ohm , tr=5 µs

dv/dt = 20 V/µs linear up to 75% VDRM

di/dt=-20 A/µs, I= 2150 A

125

200

A/µs

V/µs

µs

1000

500

µs

Q RR

I RR

I H

125

µC

Peak reverse recovery current

Holding current, typical

VR= 50 V

VD=5V, gate open circuit

500

1000

I L

Latching current, typical

VD=12V, tp=30µs

GATE

V GT

Gate trigger voltage

VD=12V

3,5

400

0,25

I GT

Gate trigger current

VD=12V

V GD

V FGM

Non-trigger gate voltage, min.

Peak gate voltage (forward)

Peak gate current

VD=VDRM

125

FGM

V RGM

P GM

P G

Peak gate voltage (reverse)

Peak gate power dissipation

Average gate power dissipation

Pulse width 100 µs

150

MOUNTING

R th(j-c)

Thermal impedance, DC

Junction to case, double side cooled

Case to heatsink, double side cooled

6,0

1,5

°C/kW

R th(c-h)

Thermal impedance

T j

Operating junction temperature

Mounting force

-30 / 125

80.0 / 100.0

3000

°C

Mass

ORDERING INFORMATION : AT940 S 29

VDRM&VRRM/100

standard specification

Page 1 of 6

12 3 4 5 6

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